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421 条记录 (耗时 0.03 秒)

    Load-generated drive, substantially no quiescent current, techniques and circuits for high speed switching of transistors
    81.
    发明授权
    Load-generated drive, substantially no quiescent current, techniques and circuits for high speed switching of transistors 有权
    负载产生的驱动器，基本上没有静态电流，用于晶体管高速切换的技术和电路

    公开(公告)号：US06861892B1

    公开(公告)日：2005-03-01

    申请号：US10350552

    申请日：2003-01-22

    申请人： Karl Edwards

    发明人： Karl Edwards

    IPC分类号： H03K17/0412 ,  H03K17/042 ,  H03K17/06 ,  H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/04126 ,  H03K17/06

    摘要： Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

    摘要翻译： 提供了用于晶体管高速切换的技术和电路。 这些技术和电路在输出设备的输出电流成比例地改变输出设备的驱动电流的同时切换输出设备。 此外，这些技术和电路提供基本上没有静态电流的开关电路。 这是通过对由输出设备传导的输出电流进行采样并使用样本作为信号来驱动输出设备完全打开或将输出设备完全关断来实现的。

    Highly configurable PLL architecture for programmable logic
    83.
    发明授权
    Highly configurable PLL architecture for programmable logic 有权
    用于可编程逻辑的高度可配置的PLL架构

    公开(公告)号：US07276943B2

    公开(公告)日：2007-10-02

    申请号：US11486565

    申请日：2006-07-13

    申请人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    发明人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/18 ,  H03L7/081 ,  H03L7/0996

    摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

    摘要翻译： 可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。 每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

    Sofa
    84.
    外观设计
    Sofa 有权

    公开(公告)号：USD551462S1

    公开(公告)日：2007-09-25

    申请号：US29233766

    申请日：2005-07-08

    申请人： Luca Ricci

    设计人： Luca Ricci

    Systems and methods for flow measurement
    85.
    发明授权
    Systems and methods for flow measurement 有权
    用于流量测量的系统和方法

    公开(公告)号：US07274621B1

    公开(公告)日：2007-09-25

    申请号：US10421065

    申请日：2003-04-23

    申请人： William B. Coney

    发明人： William B. Coney

    IPC分类号： G01F1/20 ,  G01F1/66 ,  G01P5/00

    CPC分类号： G01F1/20 ,  G01F1/66 ,  G01P5/00

    摘要： A system estimates flow parameters associated with a fluid flow encountering a bluff body. The system includes multiple sensors distributed on a surface of a bluff body. The system further includes input circuitry and a sensor processing unit. The input circuitry receives a signal from each of the multiple sensors. The sensor processing unit determines noise levels associated with each of the multiple sensors due to the fluid flow encountering the bluff body. The sensor processing unit further assigns weights to each of the multiple sensors based on the determined noise levels and estimates the fluid flow direction based on the assigned weights.

    摘要翻译： 系统估计与遇到非流线体的流体流有关的流量参数。 该系统包括分布在非流线形体的表面上的多个传感器。 该系统还包括输入电路和传感器处理单元。 输入电路接收来自多个传感器中的每一个的信号。 传感器处理单元由于遇到非流线体的流体流动而确定与多个传感器中的每一个相关联的噪声水平。 传感器处理单元还基于所确定的噪声水平对每个多个传感器分配权重，并基于分配的权重来估计流体流动方向。

    Systems and methods for beaconing in wireless networks with low probability of detection
    87.
    发明授权
    Systems and methods for beaconing in wireless networks with low probability of detection 有权
    探测概率低的无线网络中信标的系统和方法

    公开(公告)号：US07269198B1

    公开(公告)日：2007-09-11

    申请号：US10022083

    申请日：2001-11-19

    申请人： Brig Barnum Elliott ,  Warner George Harrison

    发明人： Brig Barnum Elliott ,  Warner George Harrison

    IPC分类号： H04B1/00

    CPC分类号： H04W52/322 ,  H04W4/06 ,  H04W24/00 ,  H04W40/06 ,  H04W40/246 ,  H04W48/08 ,  Y02D70/22 ,  Y02D70/322

    摘要： Systems and methods for performing neighbor discovery in a network (100) including a number of nodes are provided. A first node (110) in the network (100) generates a spread signal for alerting other nodes in the network (100) of the presence of the first node (110). The first node (110) broadcasts the signal and a second node (120) receives the signal and calculates an energy associated with the received signal. The second node (120) also determines whether the energy is greater than a threshold and identifies the first node (110) as a neighbor node when the energy is greater than the threshold.

    摘要翻译： 提供了在包括多个节点的网络（100）中执行邻居发现的系统和方法。 网络（100）中的第一节点（110）生成用于向网络（100）中的其他节点提醒第一节点（110）的存在的扩展信号。 第一节点（110）广播信号，第二节点（120）接收信号并计算与接收信号相关联的能量。 当能量大于阈值时，第二节点（120）还确定能量是否大于阈值，并将第一节点（110）识别为邻居节点。

    Method of creating a virtual window
    88.
    发明授权
    Method of creating a virtual window 有权
    创建虚拟窗口的方法

    公开(公告)号：US07262789B2

    公开(公告)日：2007-08-28

    申请号：US10350900

    申请日：2003-01-23

    申请人： Peter W. J. Jones

    发明人： Peter W. J. Jones

    IPC分类号： H04N7/00

    CPC分类号： H04N17/004 ,  F41H11/00 ,  F41H13/00 ,  G06F1/1601 ,  H04N5/23238 ,  H04N5/2628 ,  H04N17/002 ,  Y10T29/49002

    摘要： The systems and methods described herein include, among other things, a technique for calibrating the outputs of multiple sensors, such as CCD devices, that have overlapping fields of view and mapping the pixels of those outputs to the pixels of a display screen by means of a lookup table so that a user can see a selected field of view within the larger fields of view that are seen by the sensors.

    摘要翻译： 本文描述的系统和方法尤其包括用于校准具有重叠视场的多个传感器（例如CCD设备）的输出的技术，并且通过以下方式将这些输出的像素映射到显示屏的像素 查找表，使得用户可以在传感器看到的较大视野范围内看到所选择的视场。

    Read command triggered synchronization circuitry
    90.
    发明授权
    Read command triggered synchronization circuitry 有权
    读命令触发同步电路

    公开(公告)号：US07245551B2

    公开(公告)日：2007-07-17

    申请号：US10922429

    申请日：2004-08-19

    申请人： Joo S Choi

    发明人： Joo S Choi

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4096

    摘要： A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.

    摘要翻译： 存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。 时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。 因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。