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    Highly configurable PLL architecture for programmable logic
    1.
    发明授权
    Highly configurable PLL architecture for programmable logic 有权
    用于可编程逻辑的高度可配置的PLL架构

    公开(公告)号：US07098707B2

    公开(公告)日：2006-08-29

    申请号：US10797836

    申请日：2004-03-09

    申请人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    发明人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/18 ,  H03L7/081 ,  H03L7/0996

    摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

    摘要翻译： 可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。 每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

    Highly configurable PLL architecture for programmable logic
    2.
    发明授权
    Highly configurable PLL architecture for programmable logic 有权
    用于可编程逻辑的高度可配置的PLL架构

    公开(公告)号：US07276943B2

    公开(公告)日：2007-10-02

    申请号：US11486565

    申请日：2006-07-13

    申请人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    发明人： Gregory W. Starr ,  Wanli Chang ,  Kang Wei Lai ,  Mian Z. Smith ,  Richard Chang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/18 ,  H03L7/081 ,  H03L7/0996

    摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

    摘要翻译： 可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。 每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

    Techniques for compensating delays in clock signals on integrated circuits
    3.
    发明授权
    Techniques for compensating delays in clock signals on integrated circuits 有权
    补偿集成电路时钟信号延迟的技术

    公开(公告)号：US07619451B1

    公开(公告)日：2009-11-17

    申请号：US11670971

    申请日：2007-02-03

    申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

    发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0995 ,  G06F1/12 ,  H03L7/081 ,  H03L7/0812

    摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

    摘要翻译： 提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。 耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。 耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。 耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。 在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

    Loop circuits that reduce bandwidth variations
    4.
    发明授权
    Loop circuits that reduce bandwidth variations 有权
    减少带宽变化的环路电路

    公开(公告)号：US07602255B1

    公开(公告)日：2009-10-13

    申请号：US11861144

    申请日：2007-09-25

    申请人： Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

    发明人： Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0895 ,  H03L7/0812

    摘要： A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

    摘要翻译： 在集成电路上的反馈回路（例如锁相环）具有检测器，电荷泵和环路滤波器。 电荷泵响应于集成电路的过程中的变化来调节其输出电流，以减少环路带宽的变化。 电荷泵还响应于环路滤波器中的电阻器的电阻的变化来调整其输出电流，以减少环路带宽的变化。 电荷泵还可以响应于集成电路的温度变化来调节其输出电流，以减少环路带宽的变化。 集成电路上的延迟锁定环路具有相位检测器和电荷泵。 电荷泵响应于集成电路的温度和过程的变化来调整其输出电流，以减少环路带宽的变化。

    Programmable current reference circuit
    5.
    发明授权
    Programmable current reference circuit 有权
    可编程电流参考电路

    公开(公告)号：US06744277B1

    公开(公告)日：2004-06-01

    申请号：US10138685

    申请日：2002-05-03

    申请人： Wanli Chang ,  Gregory W. Starr

    发明人： Wanli Chang ,  Gregory W. Starr

    IPC分类号： H03L706

    CPC分类号： H03L7/0896 ,  H03L7/0898 ,  H03L7/18 ,  H03M1/808

    摘要： A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

    摘要翻译： 描述可编程电流参考电路。 可编程电流参考电路包括可编程电阻，其中可编程电阻可编程以提供多个电阻之一，其中多个电阻中的每一个对应于多个可编程电流参考电路输出中的一个。 在一个实施例中，可编程电流参考电路包括耦合到可编程电阻的电流源。 在一个实施例中，多个可编程电流参考电路输出包括多个参考电流。 还描述了包括可编程电流参考电路的锁相环。

    Programmable loop bandwidth in phase locked loop (PLL) circuit
    7.
    发明授权
    Programmable loop bandwidth in phase locked loop (PLL) circuit 有权
    锁相环（PLL）电路中的可编程环路带宽

    公开(公告)号：US06856180B1

    公开(公告)日：2005-02-15

    申请号：US10138595

    申请日：2002-05-03

    申请人： Gregory W. Starr ,  Wanli Chang

    发明人： Gregory W. Starr ,  Wanli Chang

    IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/18

    CPC分类号： H03L7/18 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075

    摘要： A PLL circuit is described. The PLL circuit includes: a feedback loop and a loop filter coupled to the feedback loop, where the loop filter is programmable to provide one of a plurality of bandwidths. In one embodiment, the loop filter is programmable to provide one of a plurality of resistances, each resistance of the plurality of resistances corresponding to one of the plurality of bandwidths. In one embodiment, the feedback loop includes a detector and a signal generator coupled to the detector.

    摘要翻译： 描述PLL电路。 PLL电路包括：反馈回路和耦合到反馈回路的环路滤波器，其中环路滤波器可编程以提供多个带宽中的一个。 在一个实施例中，环路滤波器可编程以提供多个电阻中的一个，多个电阻中的每个电阻对应于多个带宽之一。 在一个实施例中，反馈回路包括耦合到检测器的检测器和信号发生器。

    Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system
    8.
    发明授权
    Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system 有权
    在可编程锁相环（PLL）系统中模拟实现扩频调频

    公开(公告)号：US06798302B2

    公开(公告)日：2004-09-28

    申请号：US10138461

    申请日：2002-05-03

    申请人： Gregory W. Starr ,  Wanli Chang

    发明人： Gregory W. Starr ,  Wanli Chang

    IPC分类号： H03B2900

    CPC分类号： H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/18 ,  H03L7/1803 ,  H03M1/808 ,  H04B1/707

    摘要： A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

    摘要翻译： 描述PLL电路。 PLL电路包括：信号发生器; 以及耦合到信号发生器的扩频调制器，其中扩频调制器接收控制电压作为输入，并且响应于控制电压向信号发生器提供扩频控制电压。 在一个实施例中，扩频调制器包括至少一个选择器，其中至少一个选择器选择对应于扩展模式的多个电压电平和扩展频谱调制器的扩展百分比。