公开(公告)号：US20070059886A1

公开(公告)日：2007-03-15

申请号：US11308639

申请日：2006-04-15

Applicant: CHUN-JEN CHEN

Inventor： CHUN-JEN CHEN

IPC: H01L21/336 ,  H01L29/76

CPC classification number: G06F17/5036

Abstract: A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values inputted, and for calculating parameters of the MOSFET according to the input values. The parameter calculating system includes an operation selecting module (110), a value receiving module (120), a judging module (130), a parameter calculating module (140), and a circuit netlist generating module (150). A related method is also disclosed.

Abstract translation: 公开了一种用于自动计算MOSFET参数的系统。 参数计算系统在计算机中运行。 参数计算系统用于接收输入的值，并根据输入值计算MOSFET的参数。 参数计算系统包括操作选择模块（110），值接收模块（120），判断模块（130），参数计算模块（140）和电路网表生成模块（150）。 还公开了相关方法。

公开(公告)号：US20060268355A1

公开(公告)日：2006-11-30

申请号：US11502063

申请日：2006-08-09

Applicant: Chun-Jen Chen ,  Kuo-Jeng Wang

Inventor： Chun-Jen Chen ,  Kuo-Jeng Wang

IPC: H04N1/00

CPC classification number: H04N1/00241 ,  H04N1/00236 ,  H04N1/32358 ,  H04N2201/0015 ,  H04N2201/0049 ,  H04N2201/0462

Abstract: In accordance with the present invention, a method and a system for promoting scanning speed are provided. The method comprises steps of determining a transmission rate of a transit interface, adjusting system clock responsive to the transmission rate of the transit interface to change a data generated rate, and scanning an original to generate data at the rate controlled by the system clock. The key aspect of the present invention is by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface. Therefore, in response to the transmission rate of the transit interface, the system clock is adjusted to produce the data at a rate that can reduce the possibility of memory buffer full leading to the reduction in the time wasting on start-stop processes and therefore promote the scanning speed without requiring the increase in size of a memory buffer.

公开(公告)号：US20050219970A1

公开(公告)日：2005-10-06

申请号：US11160114

申请日：2005-06-09

Applicant: Tzu-Ming Chou ,  Kun-Hung Hsieh ,  Wei-Yu Lin ,  Yao-Lung Chuang ,  Chun-Jen Chen ,  Kuo-Jung Lan

Inventor： Tzu-Ming Chou ,  Kun-Hung Hsieh ,  Wei-Yu Lin ,  Yao-Lung Chuang ,  Chun-Jen Chen ,  Kuo-Jung Lan

IPC: G11B5/09 ,  G11B7/00 ,  G11B7/0045 ,  G11B7/005 ,  G11B7/085 ,  G11B7/09 ,  G11B19/04 ,  G11B19/26 ,  G11B27/13

CPC classification number: G11B19/041 ,  G11B7/0045 ,  G11B7/1267 ,  G11B19/04 ,  G11B19/26 ,  G11B19/28

Abstract: A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal, the frequency of buffer under-run occurrence, the temperature of the drive, the wobble jitter and the level of write power is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. If at least one of the temperature of the drive, the wobble jitter and the estimated write power exceeds the reset value before recording starts, the rotation speed of the optical disk drive is decreased before recording.

Abstract translation: 光盘驱动器的记录方法如下进行。 首先，聚焦误差信号的电平，跟踪误差信号的电平，摆动同步模式损耗，解调摆动信号的误码率，缓冲器欠载发生的频率， 驱动，检测摆动抖动和写入电平。 如果至少一个检测值超过预设值，则停止录制。 然后，光盘驱动器的旋转速度降低，并且以降低的转速恢复记录。 如果在记录开始之前驱动器的温度，摆动抖动和估计的写入功率中的至少一个超过复位值，则在记录之前光盘驱动器的转速减小。

公开(公告)号：US20050125763A1

公开(公告)日：2005-06-09

申请号：US10880903

申请日：2004-06-30

Applicant: Ko-Feng Lin ,  Yi-Hsu Chen ,  Lee-Chih Yeh ,  Chun-Jen Chen ,  Ta-Chin Chin

Inventor： Ko-Feng Lin ,  Yi-Hsu Chen ,  Lee-Chih Yeh ,  Chun-Jen Chen ,  Ta-Chin Chin

IPC: G06F13/10 ,  G06F17/50 ,  G03F9/00 ,  G21K5/00

CPC classification number: G06F17/5068

Abstract: Provided are a system and method for creating a reticle field layout (RFL). In one example, the method includes receiving information for a RFL design by a computer system directly from a user via a computer interface. The RFL design is automatically verified using predefined specification and design rules accessible to the computer system. The RFL design may be modified by adding additional features before being finalized.

Abstract translation: 提供了一种用于创建掩模版场布局（RFL）的系统和方法。 在一个示例中，该方法包括通过计算机系统直接从用户经由计算机接口接收RFL设计的信息。 使用计算机系统可访问的预定义​​规范和设计规则自动验证RFL设计。 RFL设计可以通过在定稿之前添加附加功能来修改。

公开(公告)号：US20050000807A1

公开(公告)日：2005-01-06

申请号：US10722549

申请日：2003-11-28

Applicant: Kuo-Jeng Wang ,  Chun-Jen Chen

Inventor： Kuo-Jeng Wang ,  Chun-Jen Chen

IPC: C12M1/00 ,  C12M1/40 ,  C12N9/00 ,  G01N33/48 ,  G01N33/487

CPC classification number: G01N33/48785

Abstract: A biosensor with multi-channel A/D conversion and a method thereof are provided. The present biosensor includes a chip generating a time-dependent analog signal in response to a content of a specific component of a specimen provided thereon, a multi-channel A/D converter, and a microprocessor. The multi-channel A/D converter has multiple channels simultaneously receiving the time-dependent analog signal in each sampling interval to convert the time-dependent analog signal to a set of digital signals. The microprocessor receives the sets of digital signals in a period of sampling time and determines the content of the specific component based on the sets of digital signals. The present biosensor provides a multi-channel A/D conversion for the time-dependent analog signal to improve the resolution of the determination of the content of the specific component.

Abstract translation: 提供了具有多通道A / D转换的生物传感器及其方法。 本生物传感器包括响应于其上提供的试样的特定部件的内容，多通道A / D转换器和微处理器产生时间相关模拟信号的芯片。 多通道A / D转换器具有多个通道，每个采样间隔同时接收时间相关的模拟信号，以将时间相关的模拟信号转换成一组数字信号。 微处理器在采样时间段内接收数字信号组，并根据数字信号组确定特定分量的内容。 本生物传感器为时间依赖模拟信号提供多通道A / D转换，以提高确定特定部件内容的分辨率。

公开(公告)号：US06711010B2

公开(公告)日：2004-03-23

申请号：US10095942

申请日：2002-03-13

Applicant: Ti-Li Wei ,  Chun-Jung Tsai ,  Chun-Jen Chen

Inventor： Ti-Li Wei ,  Chun-Jung Tsai ,  Chun-Jen Chen

IPC: G06F116

CPC classification number: G06K13/0825 ,  G06K13/08 ,  G06K13/0806

Abstract: A memory card ejecting structure includes an electrically insulative frame base, the frame base having a receiving unit mounted with a set of terminals for receiving a memory card and two arms forwardly extended from two opposite lateral sides of the receiving unit, the receiving unit having an endless guide groove, an ejecting member slidably mounted in the frame base and adapted for ejecting the inserted memory card out of the receiving unit, and a spring member connected between the ejecting member and one arm of the frame base, the spring member having an angled locating wire rod backwardly extended from a rear end ring thereof and positioned in the endless guide groove to hold the spring member between a stretched position and a released position.

Abstract translation: 存储卡弹出结构包括电绝缘框架基座，所述框架基座具有安装有用于接收存储卡的一组端子的接收单元和从所述接收单元的两个相对侧向前延伸的两个臂，所述接收单元具有 环形引导槽，可滑动地安装在框架基座中并适于将插入的存储卡从接收单元中排出的弹出构件以及连接在排出构件和框架基座的一个臂之间的弹簧构件，弹簧构件具有成角度 将线材从其后端环向后延伸并定位在环形引导槽中，以将弹簧构件保持在拉伸位置和释放位置之间。

公开(公告)号：US09671685B2

公开(公告)日：2017-06-06

申请号：US12976646

申请日：2010-12-22

Applicant: Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

Inventor： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

IPC: G06F17/50 ,  G03F1/72 ,  G03F1/86

CPC classification number: G03F1/72 ,  G03F1/86

Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

公开(公告)号：US20130241755A1

公开(公告)日：2013-09-19

申请号：US13596744

申请日：2012-08-28

Applicant: Chun-Jen Chen ,  Tsung-Heng Tsai ,  Tzu-Yi Tang

Inventor： Chun-Jen Chen ,  Tsung-Heng Tsai ,  Tzu-Yi Tang

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/1215

Abstract: A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC) is provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew.

Abstract translation: 提供了一种用于时间交织的模数转换器（ADC）的定时校准电路。 定时校准电路包括相关单元，自适应滤波器和延迟单元。 相关单元根据第一数字数据和第二数字数据之间的第一过零可能性分布产生第一相关系数，并且根据第二数字数据和第二数字数据之间的第二过零可能性分布产生第二相关系数 第三个数字数据。 自适应滤波器根据第一相关系数和第二相关系数之间的差产生预测的时间偏差。 延迟单元根据预测的时间偏差来校准ADC的时钟信号。

公开(公告)号：US08519512B2

公开(公告)日：2013-08-27

申请号：US11525575

申请日：2006-09-22

Applicant: Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

Inventor： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC: H01L23/544

CPC classification number: H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

公开(公告)号：US08468490B2

公开(公告)日：2013-06-18

申请号：US13315291

申请日：2011-12-09

Applicant: Dan-Chen Wu ,  Shou-Kuo Hsu ,  Cheng-Hsien Lee ,  Chun-Jen Chen

Inventor： Dan-Chen Wu ,  Shou-Kuo Hsu ,  Cheng-Hsien Lee ,  Chun-Jen Chen

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device.

Abstract translation: 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择电力线。 该方法从PCB的布局图搜索与所选择的电力线重叠的一条或多条信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线和所选电力线的属性数据，并将所搜索的信号线和所选电力线的属性数据显示在电子设备的显示装置上。