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    MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE
    81.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE 有权
    存储器件，存储器系统和控制存储器件读取电压的方法

    公开(公告)号：US20150029796A1

    公开(公告)日：2015-01-29

    申请号：US13948557

    申请日：2013-07-23

    Applicant: MYUNG-HOON CHOI ,  JAE-YONG JEONG ,  KI-TAE PARK

    Inventor： MYUNG-HOON CHOI ,  JAE-YONG JEONG ,  KI-TAE PARK

    IPC: G11C7/10 ,  G11C29/44

    CPC classification number: G11C7/1057 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44

    Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation

    Abstract translation: 存储器件包括具有多个存储器单元的存储单元阵列，以及一个页缓冲器单元，包括多个页缓冲器，其被配置为存储从不同读电压电平的多个存储单元中的一些存储单元顺序读取的多个数据段 分别对多条数据执行逻辑运算。 存储装置还包括计数单元，其被配置为基于逻辑运算的结果对存在于由不同读取电压电平定义的多个部分中的每一个中存储的存储器单元的数量进行计数

    Nonvolatile memory device, memory system, and read method thereof
    82.
    发明授权
    Nonvolatile memory device, memory system, and read method thereof 有权
    非易失存储器件，存储器系统及其读取方法

    公开(公告)号：US08665647B2

    公开(公告)日：2014-03-04

    申请号：US13302573

    申请日：2011-11-22

    Applicant: Ju Seok Lee ,  Jae Yong Jeong ,  Seung Bum Kim

    Inventor： Ju Seok Lee ,  Jae Yong Jeong ,  Seung Bum Kim

    IPC: G11C11/34

    CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

    Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

    Abstract translation: 非易失性存储器件执行用于补偿由于相邻存储单元的耦合的读取操作。 利用非易失性存储器件的读取操作，基于与所选择的存储器单元相邻的相邻存储器单元的编程状态来补偿包括在所选存储单元的读取结果中的耦合效应。 为此，在选择的存储单元被读取之前，选择性地执行相邻存储单元的读取操作。 在感测到来自所选择的存储单元的数据时，根据相邻存储单元的编程状态，根据相邻存储单元的编程状态，读取电压变化，执行所选存储单元的一个或多个读操作 。

    NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF THE SAME
    83.
    发明申请
    NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF THE SAME 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20130094292A1

    公开(公告)日：2013-04-18

    申请号：US13533999

    申请日：2012-06-27

    Applicant: SANG-SOO PARK ,  JAE-YONG JEONG

    Inventor： SANG-SOO PARK ,  JAE-YONG JEONG

    IPC: G11C16/12 ,  G11C16/04

    CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

    Abstract: A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively.

    Abstract translation: 提供了一种用于对多级单元闪存设备进行编程的方法。 所述编程方法包括：通过在第一至第i程序状态中的第一至第i程序状态中的第一存储器单元将第一编程脉冲施加到第一存储器单元 类型编程操作，并且将第二存储器单元编程为i + 1到第j编程状态之一，其中j是等于或大于3的整数，通过在第二存储器单元中施加第二编程脉冲 第二类编程操作。 第二阶梯电压，第二位线强制电压和第二类型编程操作的第二验证操作中的至少一个不同于第一阶跃电压，第一位线强制电压和第一验证操作 第一类编程操作。

    Trim circuit and semiconductor memory device comprising same
    85.
    发明授权
    Trim circuit and semiconductor memory device comprising same 有权
    修剪电路和包括其的半导体存储器件

    公开(公告)号：US08379460B2

    公开(公告)日：2013-02-19

    申请号：US12912001

    申请日：2010-10-26

    Applicant: Jae-Yong Jeong

    Inventor： Jae-Yong Jeong

    IPC: G11C7/10

    CPC classification number: G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/4402

    Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

    Abstract translation: 修剪电路包括修剪码存储单元，全局锁存单元和本地锁存单元。 修剪码存储单元存储多个修剪码，并响应于地址信号输出感测码。 全局锁存单元锁存校准代码或感测代码以产生全局输出信号。 通过对感测代码执行校准来生成校准代码。 本地锁存单元响应于地址信号反复锁存全局输出信号以产生多个修整输出信号。

    NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND READ METHOD THEREOF
    86.
    发明申请
    NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND READ METHOD THEREOF 有权
    非易失性存储器件，存储器系统及其读取方法

    公开(公告)号：US20120134208A1

    公开(公告)日：2012-05-31

    申请号：US13302573

    申请日：2011-11-22

    Applicant: Ju Seok Lee ,  Jae Yong Jeong ,  Seung Bum Kim

    Inventor： Ju Seok Lee ,  Jae Yong Jeong ,  Seung Bum Kim

    IPC: G11C16/26

    CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

    Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

    Abstract translation: 非易失性存储器件执行用于补偿由于相邻存储单元的耦合的读取操作。 利用非易失性存储器件的读取操作，基于与所选择的存储器单元相邻的相邻存储器单元的编程状态来补偿包括在所选存储单元的读取结果中的耦合效应。 为此，在选择的存储单元被读取之前，选择性地执行相邻存储单元的读取操作。 在感测到来自所选择的存储单元的数据时，根据相邻存储单元的编程状态，根据相邻存储单元的编程状态，读取电压变化，执行所选存储单元的一个或多个读操作 。

    Method of erasing data in flash memory device
    87.
    发明授权
    Method of erasing data in flash memory device 失效
    擦除闪存设备中数据的方法

    公开(公告)号：US07986565B2

    公开(公告)日：2011-07-26

    申请号：US12458502

    申请日：2009-07-14

    Applicant: Jin-Young Chun ,  Jae-Yong Jeong

    Inventor： Jin-Young Chun ,  Jae-Yong Jeong

    IPC: G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/344 ,  G11C16/3445

    Abstract: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.

    Abstract translation: 一种擦除闪速存储器件中的数据的方法，包括使用第一擦除电压擦除至少一个闪存单元中的数据; 检测所述至少一个闪存单元是否具有小于第一电压的阈值电压; 如果所述检测步骤检测到所述阈值电压小于所述第一电压，则使用大于所述第一电压的第二电压改变所述至少一个闪存单元的阈值电压来对所述至少一个闪存单元进行编程; 如果所述检测步骤检测到所述阈值电压大于所述第一电压，则保持所述至少一个闪存单元的阈值电压; 以及使用第一验证电压验证所述至少一个闪存单元。

    Reprogrammable nonvolatile memory devices and methods
    88.
    发明授权
    Reprogrammable nonvolatile memory devices and methods 失效
    可重复编程的非易失性存储器件和方法

    公开(公告)号：US07821837B2

    公开(公告)日：2010-10-26

    申请号：US12466679

    申请日：2009-05-15

    Applicant: Jin-Young Chun ,  Jae-Yong Jeong

    Inventor： Jin-Young Chun ,  Jae-Yong Jeong

    IPC: G11C11/34

    CPC classification number: G11C16/12 ,  G11C16/26 ,  G11C16/3459

    Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

    Abstract translation: 非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。 该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。 重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作 州。

    Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof
    89.
    发明授权
    Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof 有权
    具有能够被用作程序数据缓冲器的验证数据缓冲器的闪速存储器件及其方法

    公开(公告)号：US07782680B2

    公开(公告)日：2010-08-24

    申请号：US12003589

    申请日：2007-12-28

    Applicant: Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

    Inventor： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

    IPC: G11C11/34

    CPC classification number: G11C16/3454

    Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

    Abstract translation: 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

    Method of erasing data in flash memory device
    90.
    发明申请
    Method of erasing data in flash memory device 失效
    擦除闪存设备中数据的方法

    公开(公告)号：US20100118613A1

    公开(公告)日：2010-05-13

    申请号：US12458502

    申请日：2009-07-14

    Applicant: Jin-young Chun ,  Jae-yong Jeong

    Inventor： Jin-young Chun ,  Jae-yong Jeong

    IPC: G11C16/14 ,  G11C16/04 ,  G11C29/00 ,  G11C16/06

    CPC classification number: G11C16/16 ,  G11C16/344 ,  G11C16/3445

    Abstract: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.

    Abstract translation: 一种擦除闪速存储器件中的数据的方法，包括使用第一擦除电压擦除至少一个闪存单元中的数据; 检测所述至少一个闪存单元是否具有小于第一电压的阈值电压; 如果所述检测步骤检测到所述阈值电压小于所述第一电压，则使用大于所述第一电压的第二电压改变所述至少一个闪存单元的阈值电压来对所述至少一个闪存单元进行编程; 如果所述检测步骤检测到所述阈值电压大于所述第一电压，则保持所述至少一个闪存单元的阈值电压; 以及使用第一验证电压验证所述至少一个闪存单元。

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