Nonvolatile memory device, memory system, and read method thereof
    1.
    发明授权
    Nonvolatile memory device, memory system, and read method thereof 有权
    非易失存储器件,存储器系统及其读取方法

    公开(公告)号:US08665647B2

    公开(公告)日:2014-03-04

    申请号:US13302573

    申请日:2011-11-22

    IPC分类号: G11C11/34

    摘要: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

    摘要翻译: 非易失性存储器件执行用于补偿由于相邻存储单元的耦合的读取操作。 利用非易失性存储器件的读取操作,基于与所选择的存储器单元相邻的相邻存储器单元的编程状态来补偿包括在所选存储单元的读取结果中的耦合效应。 为此,在选择的存储单元被读取之前,选择性地执行相邻存储单元的读取操作。 在感测到来自所选择的存储单元的数据时,根据相邻存储单元的编程状态,根据相邻存储单元的编程状态,读取电压变化,执行所选存储单元的一个或多个读操作 。

    NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND READ METHOD THEREOF
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND READ METHOD THEREOF 有权
    非易失性存储器件,存储器系统及其读取方法

    公开(公告)号:US20120134208A1

    公开(公告)日:2012-05-31

    申请号:US13302573

    申请日:2011-11-22

    IPC分类号: G11C16/26

    摘要: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

    摘要翻译: 非易失性存储器件执行用于补偿由于相邻存储单元的耦合的读取操作。 利用非易失性存储器件的读取操作,基于与所选择的存储器单元相邻的相邻存储器单元的编程状态来补偿包括在所选存储单元的读取结果中的耦合效应。 为此,在选择的存储单元被读取之前,选择性地执行相邻存储单元的读取操作。 在感测到来自所选择的存储单元的数据时,根据相邻存储单元的编程状态,根据相邻存储单元的编程状态,读取电压变化,执行所选存储单元的一个或多个读操作 。

    Storage device and operating method of storage device
    3.
    发明授权
    Storage device and operating method of storage device 有权
    存储设备的存储设备和操作方法

    公开(公告)号:US09431122B2

    公开(公告)日:2016-08-30

    申请号:US14856695

    申请日:2015-09-17

    申请人: Ju Seok Lee

    发明人: Ju Seok Lee

    摘要: An operating method is provided which includes receiving a read command and a read address, performing a read operation about memory cells selected according to the read address, and performing a reliability verification read operation about unselected memory cells adjacent to the selected memory cells. A number of memory cells each corresponding to at least one state of an erase state and program states of the unselected memory cells is counted as a count value based on the result of the reliability verification read operation. Data read through the read operation is output to an external device and data read through the reliability verification read operation is not output to the external device.

    摘要翻译: 提供了一种操作方法,其包括接收读取命令和读取地址,执行关于根据读取地址选择的存储器单元的读取操作,以及对与所选择的存储器单元相邻的未选择存储单元进行可靠性验证读取操作。 每个对应于擦除状态的至少一个状态的存储器单元和未选择的存储器单元的程序状态的数量被计数为基于可靠性验证读取操作的结果的计数值。 通过读取操作读取的数据被输出到外部设备,通过可靠性验证读取操作读取的数据不会输出到外部设备。

    Storage device and operating method thereof

    公开(公告)号:US09881696B2

    公开(公告)日:2018-01-30

    申请号:US14925077

    申请日:2015-10-28

    申请人: Ju Seok Lee

    发明人: Ju Seok Lee

    摘要: An operating method of a storage device includes simultaneously buffering first data in a first nonvolatile memory device and a second nonvolatile memory device, simultaneously buffering second data in the second nonvolatile memory device and a third nonvolatile memory device, performing a parity operation on the first data and the second data in the second nonvolatile memory device to generate a parity, and programming the first data, the second data, and the parity into the first nonvolatile memory device, the third nonvolatile memory device, and the second nonvolatile memory device, respectively.