ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS
    82.
    发明申请
    ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 失效
    用于半导体存储器的主动驱动器控制电路

    公开(公告)号:US20100296358A1

    公开(公告)日:2010-11-25

    申请号:US12839256

    申请日:2010-07-19

    Applicant: Jong Won Lee

    Inventor: Jong Won Lee

    CPC classification number: G11C8/18 G11C7/22 G11C8/08

    Abstract: An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal.

    Abstract translation: 一种用于半导体存储装置的有源驱动器控制电路包括:异步解码单元,其可以响应于存储体选择信号被激活,当外部命令是读或写命令时,可以产生使能的读/写使能信号,并且当 启用预充电信号,禁用启用的读/写使能信号,当外部命令为活动命令时,可以响应于存储体选择信号激活的同步解码单元可以产生使能的有效使能信号,当外部 命令是预充电命令,可以产生预充电信号,并且与时钟同步地输出有源使能信号和预充电信号;以及主动驱动器控制信号生成单元,其可以响应于主动使能而产生主动驱动器控制信号 信号和读/写使能信号。

    Reliability evaluation circuit and reliability evaluation system
    83.
    发明申请
    Reliability evaluation circuit and reliability evaluation system 有权
    可靠性评估电路和可靠性评估系统

    公开(公告)号:US20100231227A1

    公开(公告)日:2010-09-16

    申请号:US12659444

    申请日:2010-03-09

    CPC classification number: G01R31/3004

    Abstract: A reliability evaluation system comprises a reliability evaluation circuit and a reliability evaluation control circuit. The reliability evaluation circuit includes a stress device array and a stress voltage generating block configured to receive a control voltage, generate stress voltages generated by using two reference voltages, and apply the stress voltages to the unit devices in a stress mode via first I/O lines according to the control voltage. The stress device array includes the unit devices that are matrix-arrayed. Each of the unit devices has a first terminal connected to one of the first I/O lines and a second terminal connected to one of second I/O lines. The reliability evaluation control circuit is configured to generate the control voltage and the two reference voltages, and test reliability of the unit devices by using the first I/O lines and the second I/O lines.

    Abstract translation: 可靠性评估系统包括可靠性评估电路和可靠性评估控制电路。 可靠性评估电路包括应力器件阵列和应力电压产生块,其被配置为接收控制电压,产生通过使用两个参考电压产生的应力电压,并且通过第一I / O将应力电压施加到应力模式中的单位器件 线根据控制电压。 应力装置阵列包括矩阵排列的单位装置。 每个单元设备具有连接到第一I / O线之一的第一端子和连接到第二I / O线之一的第二端子。 可靠性评估控制电路被配置为通过使用第一I / O线和第二I / O线来产生控制电压和两个参考电压以及单元器件的测试可靠性。

    Sub word line driving circuit
    84.
    发明申请
    Sub word line driving circuit 审中-公开
    子字线驱动电路

    公开(公告)号:US20100157716A1

    公开(公告)日:2010-06-24

    申请号:US12455749

    申请日:2009-06-05

    Applicant: Jong Won Lee

    Inventor: Jong Won Lee

    CPC classification number: G11C8/08

    Abstract: A sub word line driving circuit includes a FX driver which buffers an inverted FX signal to generate a FX signal in response to a control signal, and a sub word line driver which is supplied with the FX signal and receives a main word line signal to drive a sub word line signal.

    Abstract translation: 子字线驱动电路包括FX驱动器,其缓冲反相FX信号以响应于控制信号产生FX信号;以及副字线驱动器,其被提供有FX信号并接收主字线信号以驱动 一个子字线信号。

    Reservoir capacitor array circuit
    85.
    发明申请
    Reservoir capacitor array circuit 有权
    蓄电池阵列电路

    公开(公告)号:US20100141333A1

    公开(公告)日:2010-06-10

    申请号:US12459037

    申请日:2009-06-26

    Applicant: Jong Won Lee

    Inventor: Jong Won Lee

    Abstract: A reservoir capacitor array circuit capable of allowing an internal voltage to be maintained stably, comprises a plurality of reservoir capacitors, each of the reservoir capacitors including a switch element which is connected between a power source voltage and a prescribed node and switched in response to a test enable signal which is enabled depending on a test mode signal or whether the fuse is cut or not, and a capacitor connected between the node and a ground voltage.

    Abstract translation: 能够稳定地保持内部电压的储存器电容器阵列电路包括多个储存电容器,每个储存电容器包括开关元件,该开关元件连接在电源电压和规定的节点之间,并响应于 根据测试模式信号使能的测试使能信号或者熔丝是否被切断,以及连接在节点和接地电压之间的电容器。

    Strobe signal controlling circuit
    86.
    发明授权
    Strobe signal controlling circuit 有权
    选通信号控制电路

    公开(公告)号:US07706195B2

    公开(公告)日:2010-04-27

    申请号:US12150404

    申请日:2008-04-28

    CPC classification number: G11C7/1078 G11C7/109 G11C7/1093

    Abstract: A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.

    Abstract translation: 提供了一种选通信号控制电路,其包括初始写入控制器,其被配置为输出与时钟信号同步的在写入命令中被激活的写入脉冲信号; DQS信号输出单元,被配置为通过同步来输出写入DQS信号 初始写入控制器对时钟信号的输出信号;控制信号发生器,被配置为响应于初始写入控制器的输出信号产生控制信号;以及复位信号发生器,被配置为响应复位信号和DQS 使能信号与控制信号同步地向DQS信号输出模块输出复位信号。

    Strobe signal controlling circuit
    88.
    发明申请
    Strobe signal controlling circuit 有权
    选通信号控制电路

    公开(公告)号:US20090168564A1

    公开(公告)日:2009-07-02

    申请号:US12150404

    申请日:2008-04-28

    CPC classification number: G11C7/1078 G11C7/109 G11C7/1093

    Abstract: A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.

    Abstract translation: 提供了一种选通信号控制电路,其包括初始写入控制器,其被配置为输出与时钟信号同步的在写入命令中被激活的写入脉冲信号; DQS信号输出单元,被配置为通过同步来输出写入DQS信号 初始写入控制器对时钟信号的输出信号;控制信号发生器,被配置为响应于初始写入控制器的输出信号产生控制信号;以及复位信号发生器,被配置为响应复位信号和DQS 使能信号与控制信号同步地向DQS信号输出模块输出复位信号。

    Methods of fabricating a semiconductor device
    89.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US20090155991A1

    公开(公告)日:2009-06-18

    申请号:US12292195

    申请日:2008-11-13

    Abstract: A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    Abstract translation: 提供了制造半导体器件的接触插塞的方法,该方法包括在衬底上形成栅极图案,形成覆盖图案的上表面和侧壁的封盖图案,在衬底上形成层间绝缘层,如 层间绝缘层暴露封盖图案的上表面,并且去除封盖图案和层间绝缘层的一部分,使得封盖图案的上表面被平坦化。

    POLYPYRROLE AND SILVER VANADIUM OXIDE COMPOSITE
    90.
    发明申请
    POLYPYRROLE AND SILVER VANADIUM OXIDE COMPOSITE 有权
    POLYPYRROLE和SILVER VANADIUM OXIDE COMPOSITE

    公开(公告)号:US20090142664A1

    公开(公告)日:2009-06-04

    申请号:US12090292

    申请日:2006-10-17

    Abstract: In one embodiment of the present disclosure, a composite electrode for a battery is provided. The composite electrode includes silver vanadium oxide present in an amount from about 75 weight percent to about 99 weight percent and polypyrrole present in an amount from about 1 weight percent to about 25 weight percent.

    Abstract translation: 在本公开的一个实施例中,提供了一种用于电池的复合电极。 复合电极包括以约75重量%至约99重量%的量存在的银钒氧化物,并且存在量为约1重量%至约25重量%的聚吡咯。

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