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    Methods of fabricating a semiconductor device
    1.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20090155991A1

    公开(公告)日：2009-06-18

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Methods of fabricating a semiconductor device
    2.
    发明授权
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08084344B2

    公开(公告)日：2011-12-27

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Slurry and method for chemical-mechanical polishing
    5.
    发明申请
    Slurry and method for chemical-mechanical polishing 审中-公开
    浆料和化学机械抛光方法

    公开(公告)号：US20070145012A1

    公开(公告)日：2007-06-28

    申请号：US11542256

    申请日：2006-10-04

    申请人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： C09K13/00 ,  C03C15/00 ,  B44C1/22

    CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

    摘要： Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.

    摘要翻译： 公开了一种用于化学机械抛光操作的浆料和方法。 浆料可以含有磨料颗粒，氧化剂，pH控制剂，螯合剂和水。 浆料的粘度可以在约1.0cP-约1.05cP的范围内，使得即使在完成化学机械抛光操作之后，也可以在具有图案的区域与无图案的区域之间降低阶梯差。 在随后的光刻操作中可能不需要控制焦深（DOF）的允许率，这可以使得随后的光刻操作能够由具有相对低的DOF的光学系统进行。

    METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME
    8.
    发明申请
    METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME 失效
    形成薄膜层的方法和制造包括其的半导体器件的方法

    公开(公告)号：US20100015729A1

    公开(公告)日：2010-01-21

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same
    9.
    发明授权
    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
    形成薄铁电体层的方法和制造其的半导体器件的制造方法

    公开(公告)号：US08124526B2

    公开(公告)日：2012-02-28

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

    Methods of forming gates of semiconductor devices
    10.
    发明授权
    Methods of forming gates of semiconductor devices 有权
    形成半导体器件栅极的方法

    公开(公告)号：US08735250B2

    公开(公告)日：2014-05-27

    申请号：US13241957

    申请日：2011-09-23

    申请人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

    发明人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/28008 ,  H01L21/28105 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545

    摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

    摘要翻译： 提供了形成半导体器件的栅极的方法。 所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。 所述方法还可以包括在第一和第二凹部中形成高k层。 所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。 所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。 所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。