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1.发明申请Slurry compositions for polishing metal, methods of polishing a metal object and methods of forming a metal wiring using the same 有权用于抛光金属的浆料组合物，抛光金属物体的方法和使用其形成金属布线的方法公开(公告)号：US20090001051A1
公开(公告)日：2009-01-01
申请号：US12213941
申请日：2008-06-26
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
摘要： A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3−) and a sulfate ion (OSO3−), and an acidic aqueous solution.
摘要翻译： 用于抛光金属的浆料组合物包括聚合物抛光促进剂，所述聚合物抛光促进剂包括烃的主链和具有磺酸根离子（SO 3 - ）和硫酸根离子（OSO 3 - ）中的至少一种的侧取代基， 酸性水溶液。
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公开(公告)号：US20090155991A1
公开(公告)日：2009-06-18
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。
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3.发明授权Slurry compositions for polishing metal, methods of polishing a metal object and methods of forming a metal wiring using the same 有权用于抛光金属的浆料组合物，抛光金属物体的方法和使用其形成金属布线的方法公开(公告)号：US08048808B2
公开(公告)日：2011-11-01
申请号：US12213941
申请日：2008-06-26
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/302
摘要： A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3−) and a sulfate ion (OSO3−), and an acidic aqueous solution.
摘要翻译： 用于抛光金属的浆料组合物包括聚合物抛光促进剂，所述聚合物抛光促进剂包括烃的主链和具有磺酸根离子（SO 3 - ）和硫酸根离子（OSO 3 - ）中的至少一种的侧取代基， 酸性水溶液。
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公开(公告)号：US08084344B2
公开(公告)日：2011-12-27
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。
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公开(公告)号：US20070145012A1
公开(公告)日：2007-06-28
申请号：US11542256
申请日：2006-10-04
申请人： Joon-Sang Park , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Joon-Sang Park , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
CPC分类号： C09K3/1463 , C09G1/02 , H01L21/3212
摘要： Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.
摘要翻译： 公开了一种用于化学机械抛光操作的浆料和方法。 浆料可以含有磨料颗粒，氧化剂，pH控制剂，螯合剂和水。 浆料的粘度可以在约1.0cP-约1.05cP的范围内，使得即使在完成化学机械抛光操作之后，也可以在具有图案的区域与无图案的区域之间降低阶梯差。 在随后的光刻操作中可能不需要控制焦深（DOF）的允许率，这可以使得随后的光刻操作能够由具有相对低的DOF的光学系统进行。
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6.发明申请公开(公告)号：US20090011599A1
公开(公告)日：2009-01-08
申请号：US12167781
申请日：2008-07-03
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
IPC分类号： H01L21/304 , C09K3/14
CPC分类号： H01L21/31053 , C09G1/02 , H01L29/66583 , H01L29/66795 , H01L29/7851
摘要： Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
摘要翻译： 提供了相对于氧化硅选择性研磨氮化硅的浆料组合物，研磨氮化硅层的方法和使用其制造半导体器件的方法。 浆料组合物包括用于降低氧化物抛光速率的第一试剂，磨料颗粒和水，并且第一试剂包括聚（丙烯酸）。 浆料组合物可以具有相对于氧化硅的氮化硅相对于在半导体制造工艺中选择性研磨氮化硅层的高抛光选择性。
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7.发明申请SLURRY COMPOSITIONS FOR SELECTIVELY POLISHING SILICON NITRIDE RELATIVE TO SILICON OXIDE, METHODS OF POLISHING A SILICON NITRIDE LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开用于选择性地氧化硅氧化物的硅酸盐组合物，用于抛光氮化硅层的方法和使用其制造半导体器件的方法公开(公告)号：US20120007018A1
公开(公告)日：2012-01-12
申请号：US13240271
申请日：2011-09-22
申请人： Jong-Won LEE , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
发明人： Jong-Won LEE , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
CPC分类号： H01L21/31053 , C09G1/02 , H01L29/66583 , H01L29/66795 , H01L29/7851
摘要： Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water. The first agent includes poly(acrylic acid), The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
摘要翻译： 提供了相对于氧化硅选择性研磨氮化硅的浆料组合物，研磨氮化硅层的方法和使用其制造半导体器件的方法。 浆料组合物包括用于降低氧化物抛光速率的第一试剂，磨料颗粒和水。 第一种试剂包括聚（丙烯酸）。在半导体制造过程中，浆料组合物可以具有相对于氧化硅的氮化硅的高抛光选择性，以选择性地研磨氮化硅层。
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8.发明授权Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same 有权用于相对于氧化硅选择性研磨氮化硅的浆料组合物，抛光氮化硅层的方法和使用其制造半导体器件的方法公开(公告)号：US08043970B2
公开(公告)日：2011-10-25
申请号：US12167781
申请日：2008-07-03
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
IPC分类号： H01L21/302 , H01L21/461 , B24D3/02 , C09C1/68
CPC分类号： H01L21/31053 , C09G1/02 , H01L29/66583 , H01L29/66795 , H01L29/7851
摘要： Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
摘要翻译： 提供了相对于氧化硅选择性研磨氮化硅的浆料组合物，研磨氮化硅层的方法和使用其制造半导体器件的方法。 浆料组合物包括用于降低氧化物抛光速率的第一试剂，磨料颗粒和水，并且第一试剂包括聚（丙烯酸）。 浆料组合物可以具有相对于氧化硅的氮化硅相对于在半导体制造工艺中选择性研磨氮化硅层的高抛光选择性。
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公开(公告)号：US06875997B2
公开(公告)日：2005-04-05
申请号：US10396595
申请日：2003-03-25
申请人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
发明人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/66 , C03C25/68 , C23F1/00 , G01R31/26 , H01L21/4763 , H01L23/544 , H01L23/58
摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。
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公开(公告)号：US20050145602A1
公开(公告)日：2005-07-07
申请号：US11055505
申请日：2005-02-10
申请人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
发明人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/66 , C03C25/68 , C23F1/00 , G01R31/26 , H01L21/4763 , H01L23/544 , H01L23/58
摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
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