公开(公告)号：US07790622B2

公开(公告)日：2010-09-07

申请号：US11778038

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Jun Jung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Jun Jung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract translation: 提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制​​或以其它方式阻碍或限制后续工艺流程。

公开(公告)号：US07781276B2

公开(公告)日：2010-08-24

申请号：US12353519

申请日：2009-01-14

Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

IPC: H01L21/337

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Abstract translation: CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

公开(公告)号：US20090323150A1

公开(公告)日：2009-12-31

申请号：US12391569

申请日：2009-02-24

Applicant: Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

Inventor： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

IPC: G02B26/08

CPC classification number: G02B26/0858

Abstract: An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.

Abstract translation: 一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支柱，以支撑所述反射镜。 铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。

公开(公告)号：US07568024B2

公开(公告)日：2009-07-28

申请号：US10337316

申请日：2003-01-07

Applicant: Kyoung-Woo Lee ,  Seung-Cheon Kim ,  Sang-Wook Lim

Inventor： Kyoung-Woo Lee ,  Seung-Cheon Kim ,  Sang-Wook Lim

IPC: G06F15/173

CPC classification number: H04L41/00 ,  H04L12/2803

Abstract: A method for deciding a network manager (NM) in a home network, including the steps of comparing a priority of a current NM and a priority of a new NM when the new NM is plugged-in a home network which is controlled by the current NM and deciding a NM having a higher priority as the NM of the home network between the current NM and the new NM, can smoothly control and manage the home network by deciding a NM having a higher priority as the NM for centralized-controlling the home network.

Abstract translation: 一种用于在家庭网络中确定网络管理器（NM）的方法，包括以下步骤：当新的NM被插入由当前所控制的家庭网络时，将当前NM的优先级与新NM的优先级进行比较 NM并且将具有较高优先级的NM作为当前NM和新NM之间的归属网络的NM可以通过将具有较高优先级的NM确定为用于集中控制家庭的NM来平滑地控制和管理归属网络 网络。

公开(公告)号：US20090075474A1

公开(公告)日：2009-03-19

申请号：US12275561

申请日：2008-11-21

Applicant: Kyoung Woo Lee ,  Hong Jae Shin ,  Jae Hak Kim

Inventor： Kyoung Woo Lee ,  Hong Jae Shin ,  Jae Hak Kim

IPC: H01L21/4763

CPC classification number: H01L21/76808

Abstract: Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from the via holes without damaging or removing the interlayer dielectric layer.

Abstract translation: 提供了用于制造双镶嵌互连结构的方法，其中使用含有致孔剂（成孔剂）的牺牲材料来填充层间电介质层中的通孔，使得牺牲材料可以转化为能够快速有效地形成的多孔材料 从通孔去除而不损坏或去除层间介电层。

公开(公告)号：US20090039480A1

公开(公告)日：2009-02-12

申请号：US12187271

申请日：2008-08-06

Applicant: KYOUNG-WOO LEE ,  Andrew Tae Kim ,  Hong-Jae Shin

Inventor： KYOUNG-WOO LEE ,  Andrew Tae Kim ,  Hong-Jae Shin

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

Abstract translation: 半导体器件包括设置在衬底上的熔丝结构。 设置在熔丝结构上的层间电介质。 第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。 第一导电图案和第二导电图案设置在层间电介质上。 第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

公开(公告)号：US20090017625A1

公开(公告)日：2009-01-15

申请号：US11778038

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  JunJung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  JunJung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract translation: 提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制​​或以其它方式阻碍或限制后续工艺流程。

公开(公告)号：US20080242015A1

公开(公告)日：2008-10-02

申请号：US11691691

申请日：2007-03-27

Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

Abstract translation: 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US20070298580A1

公开(公告)日：2007-12-27

申请号：US11897417

申请日：2007-08-30

Applicant: Kyoung-woo Lee ,  Soo-geun Lee

Inventor： Kyoung-woo Lee ,  Soo-geun Lee

IPC: H01L21/20

CPC classification number: H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

Abstract translation: 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

公开(公告)号：US20070184649A1

公开(公告)日：2007-08-09

申请号：US11348428

申请日：2006-02-06

Applicant: Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

Inventor： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/31144

Abstract: Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.

Abstract translation: 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。 然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。 由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。