公开(公告)号：US07989335B2

公开(公告)日：2011-08-02

申请号：US12661885

申请日：2010-03-25

Applicant: Kyoung-Woo Lee ,  Hong-Jae Shin

Inventor： Kyoung-Woo Lee ,  Hong-Jae Shin

IPC: H01L21/44

CPC classification number: H01L27/10852 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L28/91

Abstract: In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

Abstract translation: 在形成绝缘层图案的方法中，在基板上形成绝缘层。 在绝缘层上依次形成有机层和硬掩模层。 通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。 具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。 宽度控制间隔件形成在第一和第二开口的侧壁上。 通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。 通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

公开(公告)号：US20110183516A1

公开(公告)日：2011-07-28

申请号：US13080001

申请日：2011-04-05

Applicant: Kyoung-Woo Lee

Inventor： Kyoung-Woo Lee

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (CαHβ) wherein α and β are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening. The sacrificial spacer and the damaged pattern are removed to form a first air gap between the conductive pattern and the first insulation layer pattern, and to form a second air gap between the conductive pattern and the second insulation layer.

Abstract translation: 在形成布线结构的方法中，在基板上形成第一绝缘层，所述第一绝缘层包含一组烃（CαH＆bgr），其中α和bgr; 是整数。 在第一绝缘层上形成第二绝缘层，第二绝缘层避免了一组烃。 通过蚀刻第一绝缘层和第二绝缘层，通过第一和第二绝缘层形成第一开口。 通过对与第一开口的内侧壁对应的第一绝缘层的一部分进行表面处理，形成损伤图案和第一绝缘层图案。 在损伤图案上的第一开口和第二绝缘层上形成牺牲隔离物。 在第一开口中形成导电图案。 除去牺牲隔离物和损伤图案以在导电图案和第一绝缘层图案之间形成第一气隙，并在导电图案和第二绝缘层之间形成第二气隙。

公开(公告)号：US07951712B2

公开(公告)日：2011-05-31

申请号：US12556094

申请日：2009-09-09

Applicant: Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

Inventor： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC: H01L21/44

CPC classification number: H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Abstract translation: 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US20100248436A1

公开(公告)日：2010-09-30

申请号：US12661885

申请日：2010-03-25

Applicant: Kyoung-Woo Lee ,  Hong-Jae Shin

Inventor： Kyoung-Woo Lee ,  Hong-Jae Shin

IPC: H01L21/336 ,  G03F7/20

CPC classification number: H01L27/10852 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L28/91

Abstract: In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

Abstract translation: 在形成绝缘层图案的方法中，在基板上形成绝缘层。 在绝缘层上依次形成有机层和硬掩模层。 通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。 具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。 宽度控制间隔件形成在第一和第二开口的侧壁上。 通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。 通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

公开(公告)号：US20100060966A1

公开(公告)日：2010-03-11

申请号：US12556793

申请日：2009-09-10

Applicant: Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-Jong So ,  Hong-hee Kim

Inventor： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-Jong So ,  Hong-hee Kim

IPC: G02B26/08 ,  G05B1/02 ,  G03H1/00

CPC classification number: H01L41/0825 ,  G02B26/0858 ,  H01L41/042

Abstract: An actuator using a piezoelectric element and a method of driving the same. The actuator includes at least one piezoelectric cell moving by displacement according to an input voltage, at least one piezoelectric sensor sensing the displacement of the at least one piezoelectric cell, an error detector detecting an error in the at least one piezoelectric sensor, and a feedback signal generator generating a feedback signal corresponding to the error, thereby performing micromirror driving and sensing.

Abstract translation: 使用压电元件的致动器及其驱动方法。 致动器包括至少一个根据输入电压移动的压电单元，至少一个感测至少一个压电单元的位移的压电传感器，检测至少一个压电传感器中的误差的误差检测器和反馈 信号发生器产生对应于该误差的反馈信号，由此执行微镜驱动和感测。

公开(公告)号：US20100003814A1

公开(公告)日：2010-01-07

申请号：US12556094

申请日：2009-09-09

Applicant: Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

Inventor： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Abstract translation: 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07586175B2

公开(公告)日：2009-09-08

申请号：US11551864

申请日：2006-10-23

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

IPC: H01L23/544 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

Abstract translation: 具有多层金属化结构的半导体晶片，其被制造为包括用作低电阻电镀电流路径的嵌入式互连结构，以将在晶片的外围表面区域处的金属种子层的部分进料的体电镀电流传导到 金属种子层在半导体晶片的内/中心表面区域，以实现跨晶片的芯片区域中金属电镀的均匀性。

公开(公告)号：US20090194817A1

公开(公告)日：2009-08-06

申请号：US12420936

申请日：2009-04-09

Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC: H01L27/092 ,  H01L23/48

CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

Abstract translation: 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US20090017630A1

公开(公告)日：2009-01-15

申请号：US11778039

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

IPC: H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823871

Abstract: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.

Abstract translation: 提供了在DSL（双重应力衬垫）半导体器件中形成通孔接触的半导体制造方法，其中实现改进的蚀刻工艺流程，以便能够通过双重应力衬垫结构的重叠和非重叠区域蚀刻通孔接触开口以暴露 底层的水银触点和其他设备触点，同时减轻或消除缺陷机制，例如对DSL的非重叠区域下的接触区域进行过蚀刻。

公开(公告)号：US07462507B2

公开(公告)日：2008-12-09

申请号：US10973291

申请日：2004-10-27

Applicant: Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

Inventor： Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

IPC: H01L21/00

CPC classification number: H01L23/53238 ,  G01R31/2829 ,  H01L21/76805 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687 ,  H01L31/022408 ,  H01L2924/0002 ,  H04N17/002 ,  H01L2924/00

Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.