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    Semiconductor device and methods of forming the same
    1.
    发明授权
    Semiconductor device and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08384131B2

    公开(公告)日：2013-02-26

    申请号：US12187271

    申请日：2008-08-06

    申请人： Kyoung-Woo Lee ,  Andrew Tae Kim ,  Hong-Jae Shin

    发明人： Kyoung-Woo Lee ,  Andrew Tae Kim ,  Hong-Jae Shin

    IPC分类号： H01L27/10

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

    摘要翻译： 半导体器件包括设置在衬底上的熔丝结构。 设置在熔丝结构上的层间电介质。 第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。 第一导电图案和第二导电图案设置在层间绝缘体上。 第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

    SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20090039480A1

    公开(公告)日：2009-02-12

    申请号：US12187271

    申请日：2008-08-06

    申请人： KYOUNG-WOO LEE ,  Andrew Tae Kim ,  Hong-Jae Shin

    发明人： KYOUNG-WOO LEE ,  Andrew Tae Kim ,  Hong-Jae Shin

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

    摘要翻译： 半导体器件包括设置在衬底上的熔丝结构。 设置在熔丝结构上的层间电介质。 第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。 第一导电图案和第二导电图案设置在层间电介质上。 第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

    Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns
    3.
    发明授权
    Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns 有权
    形成绝缘层图案的方法和制造包括绝缘层图案的半导体器件的方法

    公开(公告)号：US07989335B2

    公开(公告)日：2011-08-02

    申请号：US12661885

    申请日：2010-03-25

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin

    IPC分类号： H01L21/44

    CPC分类号： H01L27/10852 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L28/91

    摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

    摘要翻译： 在形成绝缘层图案的方法中，在基板上形成绝缘层。 在绝缘层上依次形成有机层和硬掩模层。 通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。 具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。 宽度控制间隔件形成在第一和第二开口的侧壁上。 通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。 通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

    Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns
    4.
    发明申请
    Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns 有权
    形成绝缘层图案的方法和制造包括绝缘层图案的半导体器件的方法

    公开(公告)号：US20100248436A1

    公开(公告)日：2010-09-30

    申请号：US12661885

    申请日：2010-03-25

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin

    IPC分类号： H01L21/336 ,  G03F7/20

    CPC分类号： H01L27/10852 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L28/91

    摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

    摘要翻译： 在形成绝缘层图案的方法中，在基板上形成绝缘层。 在绝缘层上依次形成有机层和硬掩模层。 通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。 具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。 宽度控制间隔件形成在第一和第二开口的侧壁上。 通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。 通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

    Semiconductor device and method of manufacturing the same
    6.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07417302B2

    公开(公告)日：2008-08-26

    申请号：US11174864

    申请日：2005-07-05

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

    摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

    Method of fabricating semiconductor devices having low dielectric interlayer insulation layer
    7.
    发明授权
    Method of fabricating semiconductor devices having low dielectric interlayer insulation layer 失效
    制造具有低介电层间绝缘层的半导体器件的方法

    公开(公告)号：US06936533B2

    公开(公告)日：2005-08-30

    申请号：US09994508

    申请日：2001-11-27

    申请人： Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

    发明人： Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/58

    CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3144 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

    摘要翻译： 公开了一种制造具有低介电常数的半导体器件的方法。 根据该方法，形成碳氧化硅层，用等离子体处理并图案化。 碳硅氧化物层通过涂布法或CVD法如PECVD法形成。 用等离子体处理碳氧化硅层是通过供给至少一种选自He，H 2 H 2，N 2 O，NH 3， N 2，N 2，O 2和Ar。 希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。 在封盖层进一步堆叠和图案化的情况下，希望用H 2 - 等离子体处理。 即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

    Method of forming a via contact structure using a dual damascene process
    8.
    发明授权
    Method of forming a via contact structure using a dual damascene process 有权
    使用双镶嵌工艺形成通孔接触结构的方法

    公开(公告)号：US07307014B2

    公开(公告)日：2007-12-11

    申请号：US11099534

    申请日：2005-04-06

    申请人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    发明人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808

    摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

    摘要翻译： 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

    Method of forming interconnection lines for semiconductor device
    9.
    发明授权
    Method of forming interconnection lines for semiconductor device 失效
    形成半导体器件互连线的方法

    公开(公告)号：US07192864B2

    公开(公告)日：2007-03-20

    申请号：US11049730

    申请日：2005-02-04

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

    摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

    摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。