公开(公告)号：US08102704B2

公开(公告)日：2012-01-24

申请号：US12662247

申请日：2010-04-07

Applicant: Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

Inventor： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

IPC: G11C16/32

CPC classification number: G11C7/04 ,  G11C7/18 ,  G11C7/22 ,  G11C16/32 ,  G11C2207/002

Abstract: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Abstract translation: 公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。 根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。 基于检查结果修改写操作信号。

公开(公告)号：US07952956B2

公开(公告)日：2011-05-31

申请号：US12417679

申请日：2009-04-03

Applicant: Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

Inventor： Qi Wang ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Hyun-Ho Choi

IPC: G11C8/00

CPC classification number: G11C16/08 ,  G11C8/12

Abstract: A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract translation: 半导体存储器件包括具有分成第一和第二区域的多个可变电阻存储单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

公开(公告)号：US20110110172A1

公开(公告)日：2011-05-12

申请号：US12929349

申请日：2011-01-18

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C13/0064 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C2013/0078 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

公开(公告)号：US07936619B2

公开(公告)日：2011-05-03

申请号：US12339204

申请日：2008-12-19

Applicant: Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

Inventor： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract translation: 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元 使用外部提供的升压电压。

公开(公告)号：US07920432B2

公开(公告)日：2011-04-05

申请号：US12292897

申请日：2008-11-28

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

IPC: G11C7/00

CPC classification number: G11C13/0061 ,  G11C7/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

公开(公告)号：US07909177B2

公开(公告)日：2011-03-22

申请号：US12095294

申请日：2006-11-28

Applicant: Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

Inventor： Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

IPC: B01D39/00 ,  B01D29/00

CPC classification number: B01D69/08 ,  B01D69/12 ,  B01D2323/02 ,  B01D2325/24 ,  B01D2325/36 ,  B01D2325/40 ,  Y10T428/1372

Abstract: A braid-reinforced composite hollow fiber membrane is disclosed. The braid-reinforced composite hollow fiber membrane comprising a reinforcing material of a tubular braid and a polymer resinous thin film coated on the surface of the tubular braid is characterized in that: the tubular braid comprises multifilaments made of monofilaments having a fineness of 0.01 to 0.4 denier, and the peeling strength of the tubular braid and a polymer resinous thin film coated on the surface thereof is 1 to 10 MPa. In the composite hollow fiber membrane, the fineness of the mono filaments constituting the tubular braid of the reinforcing material is small, that is, 0.01 to 0.4 denier, thus the surface area of the tubular braid contacted with the polymer resinous thin film is increased. Thus, the peeling strength of the tubular braid and the polymer resinous thin film coated on the surface thereof is excellent, and at the same time, the initial wetting property of the composite hollow fiber membrane is excellent, that is, 80 to 120%, due to a capillary tube phenomenon or the like.

Abstract translation: 公开了一种编织增强复合中空纤维膜。 包括管状编织物的增强材料和涂覆在管状编织物表面上的聚合物树脂薄膜的编织增强复合中空纤维膜的特征在于：管状编织物包含由细度为0.01至0.4的单丝制成的复丝 旦尼尔，管状编织物的剥离强度和涂布在其表面上的聚合物树脂薄膜的剥离强度为1〜10MPa。 在复合中空纤维膜中，构成增强材料的管状编织物的单丝的细度小，即0.01〜0.4旦尼尔，因此与聚合物树脂薄膜接触的管状编织物的表面积增加。 因此，管状编织物和其表面上涂覆的聚合物树脂薄膜的剥离强度优异，同时复合中空纤维膜的初始润湿性优异，即80〜120％ 由于毛细管现象等。

公开(公告)号：US07889545B2

公开(公告)日：2011-02-15

申请号：US12187550

申请日：2008-08-07

Applicant: Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho

Inventor： Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC: G11C7/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5641 ,  G11C2213/72 ,  G11C2213/79

Abstract: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.

Abstract translation: 使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。 此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。 操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。 每个阻力水平彼此不同。 在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。 在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。

公开(公告)号：US20100246239A1

公开(公告)日：2010-09-30

申请号：US12659840

申请日：2010-03-23

Applicant: Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

Inventor： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US20100220521A1

公开(公告)日：2010-09-02

申请号：US12724679

申请日：2010-03-16

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US07701757B2

公开(公告)日：2010-04-20

申请号：US11834845

申请日：2007-08-07

Applicant: Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

Inventor： Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。