公开(公告)号：US20070267695A1

公开(公告)日：2007-11-22

申请号：US11383973

申请日：2006-05-18

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792

Abstract: Methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; methods of forming a partial SOI structure which include providing a single crystal silicon substrate having a device pattern formed thereon where the device pattern comprises a non-SOI region and an SOI region having a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; structures formed by such methods; and partial silicon-on-insulator structures comprising a single crystal silicon substrate having an device pattern disposed on a surface thereof where the device pattern includes a non-SOI region and an SOI region having a protrusion, and an oxide insulation layer disposed in the device pattern where a portion of the insulation layer is disposed under the protrusion such that the protrusion is isolated from the single crystal substrate, and where the non-SOI region is not isolated from the single crystal structure.

Abstract translation: 包括提供具有形成在基板的一部分上的器件图案的单晶硅衬底的方法，其中器件图案具有突起，在突起的一部分上形成保护层，并且在突出部和突起之间形成氧化物绝缘层 使用热氧化工艺的基板; 形成部分SOI结构的方法包括提供其上形成有器件图案的器件图案的单晶硅衬底，其中器件图案包括非SOI区域和具有突起的SOI区域，在突出部分的一部分上形成保护层， 以及使用热氧化工艺在所述突起和所述基板之间形成氧化物绝缘层; 通过这种方法形成的结构; 以及部分绝缘体上硅结构，其包括具有设置在其表面上的器件图案包括非SOI区域的器件图案的单晶硅衬底和具有突起的SOI区域，以及设置在该器件中的氧化物绝缘层 其中所述绝缘层的一部分设置在所述突起下方，使得所述突起与所述单晶基板隔离，并且其中所述非SOI区域不与所述单晶结构隔离。

公开(公告)号：US07224406B2

公开(公告)日：2007-05-29

申请号：US10919559

申请日：2004-08-16

Applicant: Ming-Hsiu Lee ,  Yuan-Hao Huang

Inventor： Ming-Hsiu Lee ,  Yuan-Hao Huang

IPC: H04N5/21 ,  H04H9/64

CPC classification number: H04N9/646

Abstract: A digital signal processing system and method applied for chroma transition, wherein the method has the acts of: performing a difference process on an original chroma signal C to obtain a first difference signal C′; calculating an absolute value |C′| of the first difference signal C′; performing a difference process on the absolute value |C′| to obtain a second difference signal Ca′; determining whether the second difference signal Ca′ is a positive signal or a negative signal; wherein based on a determined result, an optimized chroma signal is generated by either mixing the original input chroma signal C with a k-delayed chroma signal, or mixing the k-delayed chroma signal C[n−k] with a 2k-delayed chroma signal C[n−2k], where k is a constant.

Abstract translation: 一种应用于色度转换的数字信号处理系统和方法，其中该方法具有以下动作：对原始色度信号C执行差分处理以获得第一差分信号C'; 计算绝对值| C'| 的第一差分信号C'; 对绝对值| C'|执行差分处理 以获得第二差分信号Ca'; 确定第二差分信号Ca'是正信号还是负信号; 其中基于确定的结果，通过将原始输入色度信号C与k延迟色度信号进行混合或将k延迟色度信号C [nk]与2k延迟色度信号C混合来产生优化的色度信号 [n-2k]，其中k是常数。

公开(公告)号：US20060279987A1

公开(公告)日：2006-12-14

申请号：US11150799

申请日：2005-06-10

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: G11C16/04

CPC classification number: G11C16/0475

Abstract: A method for analyzing the interaction between threshold states of a multiple-bit memory cell on a coordinate system is provided. The coordinate system is formed using a plurality of axes with one axis being a threshold state of a first side of a memory cell and the second axis being a threshold state of a second side of a multiple-bit memory cell. An operation is initiated on the first side of the memory cell from a start point and continues to a first target point of the first side. Then, a trace is plotted from the start point of the first side of the memory cell to a target point of the first side of the memory cell. This plot illustrates the interaction of the threshold state of the first side of the memory cell to the threshold state of the second side of the memory cell.

Abstract translation: 提供了一种用于分析坐标系上的多位存储器单元的阈值状态之间的相互作用的方法。 坐标系由多个轴构成，一个轴是存储单元的第一侧的阈值状态，第二轴是多位存储单元的第二侧的阈值状态。 从存储器单元的起始点开始操作，并且继续到第一侧的第一目标点。 然后，从存储器单元的第一侧的起始点到存储器单元的第一侧的目标点绘制迹线。 该图示出了存储器单元的第一侧的阈值状态与存储器单元的第二侧的阈值状态的相互作用。

公开(公告)号：US06964879B2

公开(公告)日：2005-11-15

申请号：US10708524

申请日：2004-03-09

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/60 ,  H01L21/768 ,  H01L27/24 ,  H01L45/00 ,  H01L21/00

CPC classification number: H01L21/76885 ,  H01L21/314 ,  H01L21/31683 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76888 ,  H01L21/76897 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1683 ,  H01L45/1691

Abstract: A method for fabricating a contact is provided. First, a substrate is provided. A patterned first material layer is formed over the substrate. The first material layer is fabricated using a conductive material. Thereafter, a treatment operation is performed to transform a portion of the first material layer into a second material layer with insulating properties. The second material layer is located on sidewall sections and a top section of the first material layer. A dielectric layer is formed over the second material layer and the substrate. A portion of the dielectric layer and the second material layer are removed to expose the first material layer. Because a treatment transformation is used to reduce the dimension of contacts, this invention eliminates the limitations associated with forming a contact through an etching process.

Abstract translation: 提供了一种用于制造触点的方法。 首先，提供基板。 在衬底上形成图案化的第一材料层。 使用导电材料制造第一材料层。 此后，执行处理操作以将第一材料层的一部分转变成具有绝缘性质的第二材料层。 第二材料层位于第一材料层的侧壁部分和顶部部分上。 在第二材料层和衬底之上形成电介质层。 去除介电层和第二材料层的一部分以露出第一材料层。 因为使用处理变换来减小触点的尺寸，所以本发明消除了通过蚀刻工艺形成接触的限制。

公开(公告)号：US20050124116A1

公开(公告)日：2005-06-09

申请号：US10728767

申请日：2003-12-08

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

IPC: H01L21/336 ,  H01L27/06 ,  H01L31/113

CPC classification number: H01L27/0688

Abstract: A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.

Abstract translation: 至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质 层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。 隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。 介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。 位线从顶视图与字线重叠，以形成大致为十字形的形状。 通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。 第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

公开(公告)号：US20050122431A1

公开(公告)日：2005-06-09

申请号：US10919559

申请日：2004-08-16

Applicant: Ming-Hsiu Lee ,  Yuan-Hao Huang

Inventor： Ming-Hsiu Lee ,  Yuan-Hao Huang

IPC: H04N1/40 ,  H04N5/21 ,  H04N9/64

CPC classification number: H04N9/646

Abstract: A digital signal processing system and method applied for chroma transition, wherein the method has the acts of: performing a difference process on an original chroma signal C to obtain a first difference signal C′; calculating an absolute value |C′| of the first difference signal C′; performing a difference process on the absolute value |C′| to obtain a second difference signal Ca′; determining whether the second difference signal Ca′ is a positive signal or a negative signal; wherein based on a determined result, an optimized chroma signal is generated by either mixing the original input chroma signal C with a k-delayed chroma signal, or mixing the k-delayed chroma signal C[n−k] with a 2k-delayed chroma signal C[n−2k], where k is a constant.

Abstract translation: 一种应用于色度转换的数字信号处理系统和方法，其中该方法具有以下动作：对原始色度信号C执行差分处理以获得第一差分信号C'; 计算绝对值| C'| 的第一差分信号C'; 对绝对值| C'|执行差分处理 以获得第二差分信号Ca'; 确定第二差分信号Ca'是正信号还是负信号; 其中基于确定的结果，通过将原始输入色度信号C与k延迟色度信号进行混合或将k延迟色度信号C [nk]与2k延迟色度信号C混合来产生优化色度信号 [n-2k]，其中k是常数。

公开(公告)号：US20050106860A1

公开(公告)日：2005-05-19

申请号：US10708524

申请日：2004-03-09

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/60 ,  H01L21/768 ,  H01L27/24 ,  H01L45/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76885 ,  H01L21/314 ,  H01L21/31683 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76888 ,  H01L21/76897 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1683 ,  H01L45/1691

Abstract: A method for fabricating a contact is provided. First, a substrate is provided. A patterned first material layer is formed over the substrate. The first material layer is fabricated using a conductive material. Thereafter, a treatment operation is performed to transform a portion of the first material layer into a second material layer with insulating properties. The second material layer is located on sidewall sections and a top section of the first material layer. A dielectric layer is formed over the second material layer and the substrate. A portion of the dielectric layer and the second material layer are removed to expose the first material layer. Because a treatment transformation is used to reduce the dimension of contacts, this invention eliminates the limitations associated with forming a contact through an etching process.

Abstract translation: 提供了一种用于制造触点的方法。 首先，提供基板。 在衬底上形成图案化的第一材料层。 使用导电材料制造第一材料层。 此后，执行处理操作以将第一材料层的一部分转变成具有绝缘性质的第二材料层。 第二材料层位于第一材料层的侧壁部分和顶部部分上。 在第二材料层和衬底之上形成电介质层。 去除介电层和第二材料层的一部分以露出第一材料层。 因为使用处理变换来减小触点的尺寸，所以本发明消除了通过蚀刻工艺形成接触的限制。

公开(公告)号：US09437266B2

公开(公告)日：2016-09-06

申请号：US13675923

申请日：2012-11-13

Applicant: Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

Inventor： Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: H01L45/00 ,  G11C11/00 ,  H01L27/24

CPC classification number: G11C11/00 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract translation: 可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。 在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。 为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。 为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。 作为焦耳加热的结果，介电层中的任何桥分解。

公开(公告)号：US08674459B2

公开(公告)日：2014-03-18

申请号：US13022588

申请日：2011-02-07

Applicant: Ming-Hsiu Lee ,  Yen-Hao Shih

Inventor： Ming-Hsiu Lee ,  Yen-Hao Shih

IPC: H01L29/78

CPC classification number: G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention describes a semiconductor cell including a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.

Abstract translation: 本发明描述了一种包括栅极，电介质层，沟道层，源极区，漏极区和氧化物区的半导体单元。 电介质层与栅极相邻。 沟道层与电介质层相邻并且形成在源极区，漏极区和氧化物区的上方。

公开(公告)号：US20140027706A1

公开(公告)日：2014-01-30

申请号：US13561558

申请日：2012-07-30

Applicant: Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

Inventor： Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

IPC: H01L27/24 ,  H03K17/975

CPC classification number: G11C13/0002 ,  G11C13/003 ,  H01L27/2409 ,  H01L43/02 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract translation: 提供了一种切换装置及其操作方法及其存储器阵列。 开关装置包括第一固体电解质，第二固体电解质和开关层。 开关层与第一固体电解质和第二固体电解质相邻。