中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

134 records (took 0.025 seconds)

    SELF-BIASING TRANSISTOR STRUCTURE AND AN SRAM CELL HAVING LESS THAN SIX TRANSISTORS
    84.
    发明申请
    SELF-BIASING TRANSISTOR STRUCTURE AND AN SRAM CELL HAVING LESS THAN SIX TRANSISTORS 审中-公开
    自偏转晶体管结构和具有不到六个晶体管的SRAM单元

    公开(公告)号：US20090026521A1

    公开(公告)日：2009-01-29

    申请号：US12240312

    申请日：2008-09-29

    Applicant: Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

    Inventor： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

    IPC: H01L29/00

    CPC classification number: H01L29/105 ,  G11C11/412 ,  H01L27/11 ,  H01L29/7838

    Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

    Abstract translation: 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元，并且在优选实施例中，具有少至两个单独的晶体管 元素。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    86.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20080099794A1

    公开(公告)日：2008-05-01

    申请号：US11748902

    申请日：2007-05-15

    Applicant: Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    Inventor： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC: H01L29/04 ,  H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    Abstract translation: 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些说明性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    Technique for providing multiple stress sources in NMOS and PMOS transistors
    88.
    发明授权
    Technique for providing multiple stress sources in NMOS and PMOS transistors 有权
    在NMOS和PMOS晶体管中提供多个应力源的技术

    公开(公告)号：US07329571B2

    公开(公告)日：2008-02-12

    申请号：US11466802

    申请日：2006-08-24

    Applicant: Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    Inventor： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/44

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

    Abstract: By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

    Abstract translation: 通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。 为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻 停止层拉伸应力。 此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

    METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY
    89.
    发明申请
    METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY 有权
    在具有预定表面形貌的半导体中增加栅格形成过程中的刻蚀能力的方法

    公开(公告)号：US20080026552A1

    公开(公告)日：2008-01-31

    申请号：US11773631

    申请日：2007-07-05

    Applicant: Martin Gerhardt ,  Martin Trentzsch ,  Markus Forsberg ,  Manfred Horstmann

    Inventor： Martin Gerhardt ,  Martin Trentzsch ,  Markus Forsberg ,  Manfred Horstmann

    IPC: H01L21/4763

    CPC classification number: H01L21/28123 ,  H01L29/66772

    Abstract: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

    Abstract translation: 在用于在半导体岛上形成晶体管的台面隔离结构中，执行附加的平面化步骤以增强栅极图案化工艺的均匀性。 在一些说明性实施例中，当栅电极材料形成在未填充的隔离沟槽上方时，栅电极材料可以例如基于CMP平坦化，以补偿高度不均匀的表面形貌。 因此，由于关键栅极图案化工艺的增强，台面隔离策略的显着优点可能与高度的可扩展性相结合。

    SOI TRANSISTOR HAVING A REDUCED BODY POTENTIAL AND A METHOD OF FORMING THE SAME
    90.
    发明申请
    SOI TRANSISTOR HAVING A REDUCED BODY POTENTIAL AND A METHOD OF FORMING THE SAME 有权
    具有减少身体潜力的SOI晶体管及其形成方法

    公开(公告)号：US20070252205A1

    公开(公告)日：2007-11-01

    申请号：US11609995

    申请日：2006-12-13

    Applicant: Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    Inventor： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    IPC: H01L27/12 ,  H01L21/336

    CPC classification number: H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

    Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

    Abstract translation: 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

Patent Agency Ranking