公开(公告)号：US08319311B2

公开(公告)日：2012-11-27

申请号：US12688939

申请日：2010-01-18

申请人： Neng-Kuo Chen ,  Cheng-Yuan Tsai ,  Kuo-Hwa Tzeng

发明人： Neng-Kuo Chen ,  Cheng-Yuan Tsai ,  Kuo-Hwa Tzeng

IPC分类号： H01L29/78

CPC分类号： H01L21/76232 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.

摘要翻译： 形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 以及执行第一沉积步骤以将第一介电材料填充到所述开口中。 然后第一介电材料凹入。 执行第二沉积步骤以用第二电介质材料填充开口的剩余部分。 第二电介质材料比第一电介质材料更致密。 第二电介质材料凹入直到第二电介质材料的顶表面低于半导体衬底的顶表面。

公开(公告)号：US20110195559A1

公开(公告)日：2011-08-11

申请号：US12703979

申请日：2010-02-11

申请人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

发明人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.

摘要翻译： 本公开的实施例包括形成浅沟槽隔离结构的方法。 提供基板。 衬底包括顶表面。 从顶表面延伸到衬底中形成沟槽。 沟槽具有侧壁和底面。 衬里氧化物层形成在侧壁和底表面上。 在等离子体环境中处理衬里氧化物层包括NF3，F2和BF2中的至少一种。 沟槽填充有介电层。

公开(公告)号：US20100261323A1

公开(公告)日：2010-10-14

申请号：US12819229

申请日：2010-06-21

申请人： Neng-Kuo Chen ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Chien-Chung Huang

IPC分类号： H01L21/8238 ,  H01L21/316

CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

摘要翻译： 公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。 首先制备半导体衬底，并且半导体衬底具有玛瑙结构，源极区和漏极区。 接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。 此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。 由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

公开(公告)号：US07777284B2

公开(公告)日：2010-08-17

申请号：US11754362

申请日：2007-05-28

申请人： Neng-Kuo Chen ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Chien-Chung Huang

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

摘要翻译： 公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。 首先制备半导体衬底，并且半导体衬底具有栅极结构，源极区和漏极区。 接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。 此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。 由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

公开(公告)号：US20100190345A1

公开(公告)日：2010-07-29

申请号：US12617463

申请日：2009-11-12

申请人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

发明人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

IPC分类号： H01L21/311 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/306

CPC分类号： H01L29/66795 ,  H01L21/31116 ,  H01L21/76232 ,  H01L29/7854

摘要： A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.

摘要翻译： 提供了具有散热片和制造方法的半导体器件。 在衬底上形成图案化掩模。 在衬底中形成沟槽，并且沟槽填充有电介质材料。 此后，去除图案化掩模并执行一个或多个蚀刻工艺以使电介质材料凹陷，其中至少一个蚀刻工艺是蚀刻工艺，该蚀刻工艺除去或防止围绕沟槽侧壁形成栅栏。 蚀刻工艺可以是例如使用NH 3和NF 3的等离子体蚀刻工艺，使用富聚合气体的蚀刻工艺或H 2蚀刻工艺。

公开(公告)号：US20100136791A1

公开(公告)日：2010-06-03

申请号：US12326099

申请日：2008-12-01

申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

IPC分类号： H01L21/308 ,  H01L21/30

CPC分类号： H01L21/0337

摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后，烘烤基板，第一硬掩模层和硬掩模。 在烘烤步骤之后，形成间隔层，其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

公开(公告)号：US07662730B2

公开(公告)日：2010-02-16

申请号：US11164488

申请日：2005-11-24

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

IPC分类号： H01L21/471

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.

摘要翻译： 公开了一种用于制造超高拉伸应力氮化物膜的方法。 首先执行PECVD处理以在衬底上沉积过渡氮化硅膜。 过渡氮化硅膜具有第一浓度的氢原子。 将过渡氮化硅膜进行UV固化，将氢原子的第一浓度降低至第二浓度的氢原子。

公开(公告)号：US07655987B2

公开(公告)日：2010-02-02

申请号：US12013482

申请日：2008-01-14

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

IPC分类号： H01L29/772

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

摘要翻译： 公开了金属氧化物半导体（MOS）晶体管器件。 MOS晶体管器件包括半导体衬底; 半导体衬底上的栅极结构; 与栅极结构相邻的半导体衬底上的源/漏区; 覆盖栅极结构和源极/漏极区域的具有小于1E22原子/ cm3的氢浓度的超高拉伸应力氮化物膜; 和超高拉伸应力氮化物膜上的层间电介质（ILD）膜。

公开(公告)号：US20100022068A1

公开(公告)日：2010-01-28

申请号：US12179892

申请日：2008-07-25

申请人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

发明人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/3125 ,  H01L21/316

摘要： A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material.

摘要翻译： 形成浅沟槽隔离区域的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 使用旋转将前体填充到开口中; 对前体进行蒸汽固化以产生电介质材料; 在蒸汽固化之后，对电介质材料进行化学机械抛光（CMP）; 并且在CMP之后，对电介质材料进行蒸汽退火。

公开(公告)号：US20100015776A1

公开(公告)日：2010-01-21

申请号：US12173263

申请日：2008-07-15

申请人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai ,  Jeffrey Junhao Xu

发明人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai ,  Jeffrey Junhao Xu

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.

摘要翻译： 提供了一种用于对浅沟槽隔离件的角进行倒角的方法。 优选实施例包括用电介质填充沟槽并使电介质凹陷以暴露邻近衬底表面的沟槽侧壁的一部分。 然后将衬底在氢环境中退火，氢环境通过硅迁移使浅沟槽隔离的角落圆。