Abstract:
A wafer is provided, and a circuit layout including a first piezoresistive device layout and a second piezoresistive device layout is formed on the front surface of the wafer. The first piezoresistive device layout includes a plurality of first nodes and the second piezoresistive device layout includes a plurality of second nodes. Subsequently, a dielectric layer is formed on the circuit layout, and the dielectric layer is patterned to expose either the first nodes or the second nodes. Thereafter, a connection pattern is formed on the dielectric layer to electrically connect the first nodes or the second nodes.
Abstract:
An IgG1 λ monoclonal antibody to the immunosuppressive drug tacrolimus has improved properties. In particular, this monoclonal antibody, designated 1H6, has reduced cross-reactivity to several tacrolimus metabolites. This antibody is suitable for performance of immunoassays such as homogeneous immunoassays to detect or determine the presence or concentration of tacrolimus in samples such as blood samples. The invention further includes derivatives of tacrolimus derivatized at a non-binding portion of the molecule useful in immunizing antibody-producing animals and in producing such monoclonal antibodies, as well as labeled derivatives of tacrolimus useful as tacrolimus analogues in such assays. The invention further includes immunoassay methods for the detection of tacrolimus and test kits useful in performing such immunoassays.
Abstract:
Methods, compositions and kits are disclosed. Enzyme conjugates of Formula I may be employed in assays for the determination of an amphetamine and/or a methamphetamine. Immunogenic conjugates of Formula I may be employed to prepare antibodies for an amphetamine and/or for a methamphetamine for use in assays for the determination of an amphetamine and/or a methamphetamine. The enzyme conjugates may also be employed to screen antibodies for use in such methods.
Abstract:
An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.
Abstract:
A riveting pliers, which includes a casing having a rear end terminating in a hand grip, a sleeve mounted in the casing, a handle pivoted to the casing, a pressure bar pivoted to the casing, and links coupled between the pressure bar and the handle for enabling the pressure bar to be turned by the handle to lift the sleeve in the casing in achieving a riveting operation, wherein the pressure bar has a middle part pivoted to the inside of the casing by a pivot, a forked front end clamped on two recessed portions at the periphery of the sleeve at two opposite sides, a forked rear end mounted with a transverse pivot and a roller on the transverse pivot; the handle has a downward sloping flange stopped at the roller at the pressure bar for imparting a pressure to the pressure bar to lift the sleeve upon each operation of the handle.
Abstract:
A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.
Abstract:
A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.
Abstract:
The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.