METHOD OF FORMING A PIEZORESISTIVE DEVICE CAPABLE OF SELECTING STANDARDS AND METHOD OF FORMING A CIRCUIT LAYOUT CAPABLE OF SELECTING SUB-CIRCUIT LAYOUTS
    81.
    发明申请
    METHOD OF FORMING A PIEZORESISTIVE DEVICE CAPABLE OF SELECTING STANDARDS AND METHOD OF FORMING A CIRCUIT LAYOUT CAPABLE OF SELECTING SUB-CIRCUIT LAYOUTS 审中-公开
    形成可选择标准的PIEZORESISTIVE设备的方法和形成可选择子电路的电路布局的方法

    公开(公告)号:US20070048889A1

    公开(公告)日:2007-03-01

    申请号:US11164331

    申请日:2005-11-18

    CPC classification number: G01L9/0042

    Abstract: A wafer is provided, and a circuit layout including a first piezoresistive device layout and a second piezoresistive device layout is formed on the front surface of the wafer. The first piezoresistive device layout includes a plurality of first nodes and the second piezoresistive device layout includes a plurality of second nodes. Subsequently, a dielectric layer is formed on the circuit layout, and the dielectric layer is patterned to expose either the first nodes or the second nodes. Thereafter, a connection pattern is formed on the dielectric layer to electrically connect the first nodes or the second nodes.

    Abstract translation: 提供晶片,并且在晶片的前表面上形成包括第一压阻器件布局和第二压阻器件布局的电路布局。 第一压阻器件布局包括多个第一节点,并且第二压阻器件布局包括多个第二节点。 随后,在电路布局上形成电介质层,并对电介质层进行图案化以暴露第一节点或第二节点。 此后,在电介质层上形成连接图案以电连接第一节点或第二节点。

    Monoclonal antibodies to tacrolimus and immunoassay methods for tacrolimus
    82.
    发明授权
    Monoclonal antibodies to tacrolimus and immunoassay methods for tacrolimus 有权
    他克莫司的单克隆抗体和他克莫司的免疫测定方法

    公开(公告)号:US07078495B1

    公开(公告)日:2006-07-18

    申请号:US09368010

    申请日:1999-08-03

    CPC classification number: A61K51/1093 C07K16/1292 Y10S436/815

    Abstract: An IgG1 λ monoclonal antibody to the immunosuppressive drug tacrolimus has improved properties. In particular, this monoclonal antibody, designated 1H6, has reduced cross-reactivity to several tacrolimus metabolites. This antibody is suitable for performance of immunoassays such as homogeneous immunoassays to detect or determine the presence or concentration of tacrolimus in samples such as blood samples. The invention further includes derivatives of tacrolimus derivatized at a non-binding portion of the molecule useful in immunizing antibody-producing animals and in producing such monoclonal antibodies, as well as labeled derivatives of tacrolimus useful as tacrolimus analogues in such assays. The invention further includes immunoassay methods for the detection of tacrolimus and test kits useful in performing such immunoassays.

    Abstract translation: 针对免疫抑制药物他克莫司的IgG1λ1λ单克隆抗体具有改善的性质。 特别地,称为1H6的单克隆抗体具有降低的几种他克莫司代谢物的交叉反应性。 该抗体适用于进行免疫测定,例如均匀免疫测定,以检测或确定样品如血液样品中他克莫司的存在或浓度。 本发明还包括在该分子的非结合部分衍生的他克莫司的衍生物,其可用于免疫产生抗体的动物和产生此类单克隆抗体,以及在该测定中用作他克莫司类似物的他克莫司的标记衍生物。 本发明还包括用于检测他克莫司的免疫测定方法和用于进行这种免疫测定的试剂盒。

    Multi-unit charger
    83.
    外观设计
    Multi-unit charger 有权
    多单元充电器

    公开(公告)号:USD520447S1

    公开(公告)日:2006-05-09

    申请号:US29224087

    申请日:2005-02-24

    Applicant: Lan-Ting Liu

    Designer: Lan-Ting Liu

    Inter-wiring-layer capacitors
    86.
    发明授权
    Inter-wiring-layer capacitors 有权
    布线层电容器

    公开(公告)号:US06794694B2

    公开(公告)日:2004-09-21

    申请号:US09742314

    申请日:2000-12-21

    Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

    Abstract translation: 集成电路包括其上形成有半导体器件的半导体衬底及其上,位于衬底上的第一布线层,位于第一布线层上的第二布线层和电容器。 电容器具有延伸穿过第二布线层和至少部分第一布线层的金属基电荷存储电极。 布线层具有嵌入其中的互连线。

    Riveting pliers
    87.
    发明授权
    Riveting pliers 失效
    铆钉钳

    公开(公告)号:US6085400A

    公开(公告)日:2000-07-11

    申请号:US383360

    申请日:1999-08-26

    Applicant: Yang-Ting Liu

    Inventor: Yang-Ting Liu

    CPC classification number: B21J15/386 B21J15/043 Y10T29/5373

    Abstract: A riveting pliers, which includes a casing having a rear end terminating in a hand grip, a sleeve mounted in the casing, a handle pivoted to the casing, a pressure bar pivoted to the casing, and links coupled between the pressure bar and the handle for enabling the pressure bar to be turned by the handle to lift the sleeve in the casing in achieving a riveting operation, wherein the pressure bar has a middle part pivoted to the inside of the casing by a pivot, a forked front end clamped on two recessed portions at the periphery of the sleeve at two opposite sides, a forked rear end mounted with a transverse pivot and a roller on the transverse pivot; the handle has a downward sloping flange stopped at the roller at the pressure bar for imparting a pressure to the pressure bar to lift the sleeve upon each operation of the handle.

    Abstract translation: 一种铆接钳子,其包括具有终止于手柄的后端的壳体,安装在壳体中的套筒,枢转到壳体的手柄,枢转到壳体的压力杆,以及联接在压力杆和手柄之间的连杆 为了使压力杆能够通过手柄转动以提升套管中的套筒以实现铆接操作,其中压杆具有通过枢轴枢转到壳体内部的中间部分,夹紧在两个上的叉形前端 在两个相对侧的套筒的周边处的凹部,在横向枢轴上安装有横向枢轴和辊的叉形后端; 手柄具有向下倾斜的凸缘,其在压杆处停止在辊处,用于在每个手柄的操作时向压力杆施加压力以提升套筒。

    Complementary field effect devices for eliminating or reducing diode
effect
    88.
    发明授权
    Complementary field effect devices for eliminating or reducing diode effect 失效
    用于消除或减少二极管效应的互补场效应器件

    公开(公告)号:US6054722A

    公开(公告)日:2000-04-25

    申请号:US848141

    申请日:1997-04-28

    CPC classification number: H01L27/1108 Y10S257/903 Y10S257/904

    Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

    Abstract translation: 由PMOS TFT晶体管和NMOS FET晶体管构成的互补器件使用导电层来分流晶体管的漏极区以消除任何有害的二极管或p-n结效应。 当使用互补器件来设计具有NMOS下拉晶体管的SRAM单元时,使用导电层可显着提高PMOS TFT的电流驱动能力。

    Process for producing multi-level metallization in an integrated circuit
    89.
    发明授权
    Process for producing multi-level metallization in an integrated circuit 失效
    在集成电路中生产多级金属化的工艺

    公开(公告)号:US5956618A

    公开(公告)日:1999-09-21

    申请号:US828155

    申请日:1997-03-27

    CPC classification number: H01L21/76838 Y10S438/942

    Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

    Abstract translation: 公开了一种用于制造多电平集成电路的方法,其利用网格图案,从其中选择性地去除与金属层相对应的部分以形成掩模,其随后用于在金属线之间的开放区域中沉积虚拟特征,从而 允许在金属层和虚拟特征上沉积基本上平面的电介质表面。

    Thin film transistor having increased effective channel width
    90.
    发明授权
    Thin film transistor having increased effective channel width 失效
    薄膜晶体管具有增加的有效沟道宽度

    公开(公告)号:US5656822A

    公开(公告)日:1997-08-12

    申请号:US520087

    申请日:1995-08-28

    CPC classification number: H01L29/78696 H01L29/42384

    Abstract: The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

    Abstract translation: 薄膜晶体管的上覆通道层的纵向边缘基本上与下面的多晶硅栅极层的纵向边缘对准。 作为通道和栅极层的在线布置的结果,集成区域被最小化,从而实现最佳的集成密度。 由于从多晶硅栅极的侧壁部分增加的沟道宽度的结果,源极到漏极电流增加,这可能由于主体(沟道)层在一个纵向边缘上的允许的横向延伸 由于光刻或处理三角形中的未对准而导致的沟道栅极层。

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