公开(公告)号：US5438006A

公开(公告)日：1995-08-01

申请号：US176600

申请日：1994-01-03

Applicant: Chorng-Ping Chang ,  Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

Inventor： Chorng-Ping Chang ,  Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8232

CPC classification number: H01L21/28123 ,  Y10S148/105

Abstract: An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

Abstract translation: 通过使用图案化的氧化物硬掩模对下面的金属层进行图案来制造具有降低栅极叠层的集成电路器件。 去除氧化物掩模，随后使用图案化的金属作为掩模来蚀刻多晶硅层。

公开(公告)号：US5420058A

公开(公告)日：1995-05-30

申请号：US160600

申请日：1993-12-01

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

IPC: H01L23/522 ,  H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/2257 ,  H01L29/0847 ,  H01L29/456

Abstract: A field effect transistor is fabricated with an ion implanted silicide layer and a conducting diffusion barrier pad layer that acts as a diffusion mask. The dopants from the silicide layer are diffused into the substrate to form shallow source/drain regions.

Abstract translation: 用离子注入硅化物层和用作扩散掩模的导电扩散阻挡层层制造场效应晶体管。 来自硅化物层的掺杂剂扩散到衬底中以形成浅的源极/漏极区域。

公开(公告)号：US5956618A

公开(公告)日：1999-09-21

申请号：US828155

申请日：1997-03-27

Applicant: Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

Inventor： Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/027 ,  H01L21/304

CPC classification number: H01L21/76838 ,  Y10S438/942

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract translation: 公开了一种用于制造多电平集成电路的方法，其利用网格图案，从其中选择性地去除与金属层相对应的部分以形成掩模，其随后用于在金属线之间的开放区域中沉积虚拟特征，从而 允许在金属层和虚拟特征上沉积基本上平面的电介质表面。

公开(公告)号：US5656822A

公开(公告)日：1997-08-12

申请号：US520087

申请日：1995-08-28

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/78696 ,  H01L29/42384

Abstract: The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

Abstract translation: 薄膜晶体管的上覆通道层的纵向边缘基本上与下面的多晶硅栅极层的纵向边缘对准。 作为通道和栅极层的在线布置的结果，集成区域被最小化，从而实现最佳的集成密度。 由于从多晶硅栅极的侧壁部分增加的沟道宽度的结果，源极到漏极电流增加，这可能由于主体（沟道）层在一个纵向边缘上的允许的横向延伸 由于光刻或处理三角形中的未对准而导致的沟道栅极层。

公开(公告)号：US5625200A

公开(公告)日：1997-04-29

申请号：US572196

申请日：1995-12-14

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract translation: 由PMOS TFT晶体管和NMOS FET晶体管构成的互补器件使用导电层来分流晶体管的漏极区以消除任何有害的二极管或p-n结效应。 当使用互补器件来设计具有NMOS下拉晶体管的SRAM单元时，使用导电层可显着提高PMOS TFT的电流驱动能力。

公开(公告)号：US5521861A

公开(公告)日：1996-05-28

申请号：US326575

申请日：1994-10-20

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu

IPC: G11C11/412 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/1108 ,  Y10S257/903

Abstract: A six-transistor SRAM of a high-density memory comprises two thin-film n-channel pull-down transistors and four conventional p-channel load and access transistors. As embodied in a semiconductor chip, the cell is simpler than priorly known six-transistor cells and is relatively immune from the deleterious effects of sodium ions and hot-carrier aging.

Abstract translation: 高密度存储器的六晶体管SRAM包括两个薄膜n沟道下拉晶体管和四个常规的p沟道负载和存取晶体管。 如体现在半导体芯片中，电池比先前已知的六晶体管电池简单，并且相对地免受钠离子和热载体老化的有害影响。

公开(公告)号：US5395787A

公开(公告)日：1995-03-07

申请号：US160701

申请日：1993-12-01

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814

Abstract: Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.

Abstract translation: 浅连接n沟道场效应晶体管和p沟道场效应晶体管由单个离子注入形成为保形硅化钨层。 虽然磷和硼被注入到相同的硅化物区域中，但磷防止硼向外扩散。

公开(公告)号：US5407859A

公开(公告)日：1995-04-18

申请号：US159897

申请日：1993-12-01

Applicant: Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

Inventor： Kuo-Hua Lee ,  Chun-Ting Liu ,  Ruichen Liu

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L21/44

CPC classification number: H01L29/66575 ,  H01L21/76895

Abstract: A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.

Abstract translation: 制造场效应晶体管，其具有使用具有亚光刻间隔的图案化电介质作为蚀刻掩模来图案化的窗口焊盘层。 晶体管的理想属性包括小结电容。

公开(公告)号：US20050230784A1

公开(公告)日：2005-10-20

申请号：US10341777

申请日：2003-01-14

Applicant: Yang Yang ,  Chun-Ting Liu ,  Rose Kopf ,  Chen-Jung Chen ,  Lay-Lay Chua

Inventor： Yang Yang ,  Chun-Ting Liu ,  Rose Kopf ,  Chen-Jung Chen ,  Lay-Lay Chua

IPC: G02B6/10 ,  G02B6/12 ,  G02B6/122 ,  G02B6/26 ,  H01L29/00 ,  H01L27/102

CPC classification number: G02B6/10 ,  G02B6/12004 ,  G02B6/1221 ,  G02B6/26 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12069 ,  G02B2006/12097 ,  G02B2006/12176 ,  G02B2006/12197

Abstract: The present invention provides a method for adhering dielectric layers to metals, in particular inert metals, using an adhesive layer comprising silicon-rich silicon nitride. Good adhesion is achieved at temperatures of less than 300° C., thereby facilitating the fabrication of semiconductor structures containing II-VI and III-V semiconductors.

Abstract translation: 本发明提供一种使用包含富硅氮化硅的粘合剂层将电介质层粘附到金属，特别是惰性金属的方法。 在低于300℃的温度下实现良好的附着力，从而有助于制造含有II-VI和III-V半导体的半导体结构。

公开(公告)号：US20050156195A1

公开(公告)日：2005-07-21

申请号：US11079166

申请日：2005-03-14

Applicant: Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Houtsma ,  Rose Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

Inventor： Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Houtsma ,  Rose Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/66318 ,  H01L29/7371

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.