摘要:
A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.
摘要:
The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.
摘要:
An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.
摘要:
A field effect transistor is fabricated with an ion implanted silicide layer and a conducting diffusion barrier pad layer that acts as a diffusion mask. The dopants from the silicide layer are diffused into the substrate to form shallow source/drain regions.
摘要:
A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.
摘要:
A six-transistor SRAM of a high-density memory comprises two thin-film n-channel pull-down transistors and four conventional p-channel load and access transistors. As embodied in a semiconductor chip, the cell is simpler than priorly known six-transistor cells and is relatively immune from the deleterious effects of sodium ions and hot-carrier aging.
摘要:
Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.
摘要:
A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.
摘要:
An electrophoretic display and a driving method thereof are provided. The electrophoretic display includes a display panel, a storage unit and a timing controller. The display panel has a plurality of sub pixels. The storage unit stores a plurality of sets of multiple-grayscale driving waveforms, in which the driving voltage scales of driving waveforms corresponding to a same grayscale in the sets of multiple-grayscale driving waveforms are different from each other. The timing controller is coupled to the storage unit and the display panel and receives an image signal, and when the image signal transmits a multiple-grayscale frame, the timing controller sequentially adopts the sets of multiple-grayscale driving waveforms to drive the sub pixels.
摘要:
A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.