公开(公告)号：US06303801B1

公开(公告)日：2001-10-16

申请号：US09517058

申请日：2000-03-02

申请人： Tomoyuki Suzuki ,  Toshio Sasaki

发明人： Tomoyuki Suzuki ,  Toshio Sasaki

IPC分类号： C07C5004

CPC分类号： C07C37/16 ,  Y02P20/544 ,  C07C39/08

摘要： A process for producing an alkyl-substituted hydroquinone, wherein said process comprises reacting a hydroquinone compound represented by the general formula (1) wherein R1 and R2 independently represent a hydrogen atom or a straight or branched chain alkyl group having 1 to 10 carbon atoms, R independently represent a straight or branched chain alkyl group having 1 to 10 carbon atoms and n represents an integer of 0 to 2, with a monohydric or dihydric alcohol in the presence of a catalyst and under the condition in which said alcohol is in a supercritical state by substitution of at least one hydrogen atom on the aromatic ring in said hydroquinone compound.

摘要翻译： 一种制备烷基取代氢醌的方法，其中所述方法包括使通式（1）表示的氢醌化合物，其中R1和R2独立地表示氢原子或具有1-10个碳原子的直链或支链烷基， R独立地表示碳原子数1〜10的直链或支链烷基，n表示0〜2的整数，在一种催化剂的存在下，在一元醇或二元醇中，所述醇处于超临界状态 通过在所述氢醌化合物中的芳香环上的至少一个氢原子取代来进行。

公开(公告)号：US06301184B1

公开(公告)日：2001-10-09

申请号：US09480695

申请日：2000-01-11

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C7/1045

摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。

公开(公告)号：US06201735B1

公开(公告)日：2001-03-13

申请号：US09362719

申请日：1999-07-29

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 此外，因为负电压被施加到字线，所以可以降低编程数据时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

公开(公告)号：US6103841A

公开(公告)日：2000-08-15

申请号：US841646

申请日：1997-04-30

申请人： Takeshi Ebara ,  Koji Mizunuma ,  Toshio Sasaki ,  Kazuki Wakamatsu ,  Junichi Kimura ,  Yoichi Obata

发明人： Takeshi Ebara ,  Koji Mizunuma ,  Toshio Sasaki ,  Kazuki Wakamatsu ,  Junichi Kimura ,  Yoichi Obata

IPC分类号： C08F4/58 ,  C08F4/645 ,  C08F4/658 ,  C08F10/00 ,  C08F110/06

CPC分类号： C08F110/06 ,  C08F10/00

摘要： An .alpha.-olefin polymer well balanced between stiffness, stickiness, processability, etc., which intrinsic viscosity [.eta.] is in the range of from 0.5 to 10 and which 20.degree. C. xylene-soluble fraction (CXS) content (% by weight) and 105.degree. C. xylene-insoluble fraction (XIS) content (% by weight) satisfy a condition of XIS.ltoreq.70.00-3.64CXS, provided that CXS is not smaller than 0 and not greater than 15; a specified .alpha.-olefin polymerizing catalyst for producing the polymer; a process for producing the polymer using the specified .alpha.-olefin polymerizing catalyst; a polypropylene for use in the production of a biaxially oriented film excellent in stretchability and satisfying the conditions (1)-(3) mentioned below; and a biaxially oriented film excellent in stiffness and dimensional stability obtained by stretching the polypropylene:(1) the content of 20.degree. C. xylene-soluble fraction (CXS) is 3.5% by weight or less,(2) the content of 20.degree. C. xylene-soluble fraction (CXS, % by weight) and the content of 105.degree. C. xylene-insoluble fraction (XIS, % by weight) satisfy the following condition:XIS.ltoreq.70.00-3.64CXS,and(3) melt flow rate (MFR) at 230.degree. C. is from 0.5 to 10.0 g/10 minutes.

摘要翻译： 一种在硬度，粘性，加工性等方面均衡的α-烯烃聚合物，其特性粘度η在0.5至10的范围内，20℃的二甲苯可溶级分（CXS）含量（重量％ ）和105℃，二甲苯不溶级分（XIS）含量（重量％）满足XIS≤70.00-3.64CXS的条件，条件是CXS不小于0且不大于15; 用于制备聚合物的特定的α-烯烃聚合催化剂; 使用特定的α-烯烃聚合催化剂制备聚合物的方法; 用于制造拉伸性优异且满足下述条件（1） - （3）的双轴取向膜的聚丙烯; 和通过拉伸聚丙烯获得的刚性和尺寸稳定性优异的双轴取向膜：（1）20℃二甲苯可溶级分（CXS）的含量为3.5重量％以下，（2）20℃的含量 C.二甲苯可溶级分（CXS，重量％）和105℃二甲苯不溶级分（XIS，重量％）的含量满足下列条件：XIS = 70.00-3.64CXS，（3） 230℃下的熔体流动速率（MFR）为0.5〜10.0g / 10分钟。

公开(公告)号：US6101123A

公开(公告)日：2000-08-08

申请号：US288313

申请日：1999-04-08

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C8/08 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory essentially consisting of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 特别是由于用于字线的负电压，可以降低编程数据时的漏极电压，从而可以减轻沟道部分的栅极氧化膜的劣化。

公开(公告)号：US5818792A

公开(公告)日：1998-10-06

申请号：US804683

申请日：1997-02-25

申请人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

发明人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G01C13/00

CPC分类号： G11C29/80 ,  G11C29/74 ,  G11C29/808 ,  G11C29/832

摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

摘要翻译： 第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障 在记忆垫单位。 电源基本上被切断供给故障存储器垫。

公开(公告)号：US5469390A

公开(公告)日：1995-11-21

申请号：US301284

申请日：1994-09-06

申请人： Toshio Sasaki ,  Toshihiro Tanaka

发明人： Toshio Sasaki ,  Toshihiro Tanaka

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808

摘要： In a semiconductor memory system including a plurality of memory chips, a spare memory is shared among the memory chips. For such a purpose, a common redundant circuit and an external terminal capable of accessing to a spare memory are added to a semiconductor memory system, and a first region for storing a defect address in each memory of the semiconductor memory system and a second region for storing a defect address of the system of the object having the same structure as the first region are provided in the redundant circuit. With this, even when the defect of a normal memory of the semiconductor memory system can not be replaced with the spare memory of the system itself, replacement is made possible with other system having the same structure. Accordingly, the yield of the semiconductor memory system can be increased, and the reliability is also increased.

摘要翻译： 在包括多个存储器芯片的半导体存储器系统中，在存储器芯片之间共享备用存储器。 为了这样的目的，能够访问备用存储器的公共冗余电路和外部终端被添加到半导体存储器系统中，并且第一区域用于在半导体存储器系统的每个存储器中存储缺陷地址，第二区域用于 存储具有与第一区域相同结构的对象的系统的缺陷地址设置在冗余电路中。 由此，即使半导体存储器系统的正常存储器的缺陷不能用系统本身的备用存储器替换，也可以用具有相同结构的其他系统进行替换。 因此，可以提高半导体存储器系统的产量，并且还提高可靠性。

公开(公告)号：US5422856A

公开(公告)日：1995-06-06

申请号：US203303

申请日：1994-03-01

申请人： Toshio Sasaki ,  Toshihiro Tanaka ,  Masataka Kato

发明人： Toshio Sasaki ,  Toshihiro Tanaka ,  Masataka Kato

IPC分类号： G06F12/06 ,  G06F12/00 ,  G11C16/02 ,  G11C16/10 ,  G11C17/00 ,  G11C8/00

CPC分类号： G11C16/102

摘要： To effect erase and program operations, i.e., rewrite of the non-volatile memory device efficiently with small electric power consumption and at high speed, a plurality of memory blocks that have a plurality of sectors and that each include a plurality of non-volatile memory cells are connected to buffer memories having at least the same memory capacity as a sector, and a read/write circuit generates internal addresses and timing for selecting sectors according to the external address and timing signals to control the read-out and rewrite of data between the sectors corresponding to the internal addresses and the buffer memories corresponding to the sectors, wherein the read/write circuit selects the sectors at timings shifted from one another and erases or programs the data in the selected sector in order to rewrite the data.

摘要翻译： 为了实现擦除和编程操作，即以小功耗和高速度有效地重写非易失性存储器件，具有多个扇区的多个存储器块，并且每个存储块中的每一个包括多个非易失性存储器 单元被连接到具有至少与扇区相同的存储容量的缓冲存储器，并且读/写电路根据外部地址和定时信号产生用于选择扇区的内部地址和定时，以控制数据的读出和重写 对应于内部地址的扇区和对应于扇区的缓冲存储器，其中读/写电路在彼此偏移的定时中选择扇区，并擦除或编程所选扇区中的数据，以重写数据。

公开(公告)号：US4940682A

公开(公告)日：1990-07-10

申请号：US262786

申请日：1988-10-26

申请人： Toshio Sasaki ,  Takeshi Ebara ,  Kiyoshi Kawai

发明人： Toshio Sasaki ,  Takeshi Ebara ,  Kiyoshi Kawai

IPC分类号： B62M3/00 ,  C08F4/60 ,  C08F4/64 ,  C08F4/654 ,  C08F10/00

CPC分类号： C08F10/00 ,  Y10S526/904 ,  Y10S526/908

摘要： A solid catalyst component for olefin polymerization which comprises a catalyst component comprising at least titanium and chlorine fixed onto a porous substance of which the pore volume, at a pore radius in a range of from 200 to 2,000 .ANG., is 0.3 cc/g or more, said pore volume is 35% or more of the pore volume at a pore radius in a range of from 35 to 75,000 .ANG., the average particle diameter is from 5 to 300 .mu.m, the geometrical standard deviation of the particle size distribution is 2 or less and the solubility in toluene at 100.degree. C. is 30 wt. % or less.

公开(公告)号：US4280065A

公开(公告)日：1981-07-21

申请号：US969269

申请日：1978-12-14

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K19/082 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K3/01 ,  H03K19/08

CPC分类号： H03K19/09429 ,  H03K19/0823 ,  H03K19/09448 ,  H03K5/023

摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).

摘要翻译： 本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个 。 三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑 电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。 外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。