公开(公告)号：US20050233525A1

公开(公告)日：2005-10-20

申请号：US10825872

申请日：2004-04-16

申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

公开(公告)号：US20050224907A1

公开(公告)日：2005-10-13

申请号：US11146661

申请日：2005-06-07

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

摘要： A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

公开(公告)号：US06949769B2

公开(公告)日：2005-09-27

申请号：US10958472

申请日：2004-10-04

申请人： Chenming Hu ,  Yee-Chia Yeo

发明人： Chenming Hu ,  Yee-Chia Yeo

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L31/0256

CPC分类号： H01L29/78 ,  H01L29/49

摘要： A MOSFET has greatly reduced leakage current between the gate electrode and the channel, source and drain regions. The gate electrode materials have lower electron affinities than the channel, source and drain regions. Gate electrode materials with negative electron affinities can also be used. The use of these gate electrode materials enables the band structures of the gate electrode and the other regions to be aligned in a manner that eliminates tunneling states for carriers tunneling between the gate and the body of the device.

摘要翻译： MOSFET大大减少了栅极电极和沟道，源极和漏极区域之间的漏电流。 栅电极材料具有比沟道，源极和漏极区更低的电子亲和力。 也可以使用具有负电子亲和力的栅电极材料。 使用这些栅极电极材料能够使栅电极和其它区域的带结构以排除隧道状态的方式排列，以便在器件的栅极和主体之间隧穿。

公开(公告)号：US06936881B2

公开(公告)日：2005-08-30

申请号：US10628020

申请日：2003-07-25

申请人： Yee-Chia Yeo ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01G4/228 ,  H01L21/00 ,  H01L21/02 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/84 ,  H01L27/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L29/92 ,  H01L29/94

CPC分类号： H01L27/0805 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/65 ,  H01L29/66181 ,  H01L29/94 ,  Y10S257/905 ,  Y10S257/908

摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

公开(公告)号：US06911379B2

公开(公告)日：2005-06-28

申请号：US10379873

申请日：2003-03-05

申请人： Yee-Chia Yeo ,  Wen-Chin Lee

发明人： Yee-Chia Yeo ,  Wen-Chin Lee

IPC分类号： H01L21/762 ,  H01L29/10 ,  H01L29/786 ,  H10L21/20 ,  H10L21/36

CPC分类号： H01L29/7842 ,  H01L21/76254 ,  H01L29/1054 ,  H01L29/78654

摘要： A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.

摘要翻译： 公开了一种形成绝缘体上的应变硅衬底的方法。 目标晶片在基板上包括绝缘体层。 施主晶片包括具有不同于硅的晶格常数的晶格常数的体半导体衬底和在体半导体衬底上形成的应变硅层。 施主晶片的顶表面结合到目标晶片的顶表面。 然后将应变硅层从施主晶片分离，使得应变硅层粘附到目标晶片。 然后可以加强应变硅层和目标晶片之间的结合。

公开(公告)号：US20050121706A1

公开(公告)日：2005-06-09

申请号：US11031703

申请日：2005-01-07

申请人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0392 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775

摘要： In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

公开(公告)号：US06879000B2

公开(公告)日：2005-04-12

申请号：US10384253

申请日：2003-03-08

申请人： Yee-Chia Yeo

发明人： Yee-Chia Yeo

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L27/1203

摘要： A semiconductor-on-insulator chip is provided which includes a substrate that is formed of an electrically insulating material; a semiconducting layer overlying the substrate; a first region in the semiconducting layer that has a first thickness, the first region includes silicon regions defined by a shallow trench isolation; and a second region in the semiconducting layer that has a second thickness, the second region includes active regions defined by mesa isolation.

摘要翻译： 提供一种绝缘体上半导体芯片，其包括由电绝缘材料形成的基板; 覆盖衬底的半导体层; 所述半导体层中具有第一厚度的第一区域，所述第一区域包括由浅沟槽隔离限定的硅区域; 以及具有第二厚度的所述半导体层中的第二区域，所述第二区域包括由台面隔离限定的有源区域。

公开(公告)号：US20050074932A1

公开(公告)日：2005-04-07

申请号：US10678710

申请日：2003-10-03

申请人： Chuan-Yi Lin ,  Yee-Chia Yeo

发明人： Chuan-Yi Lin ,  Yee-Chia Yeo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.

摘要翻译： 提供了具有多个硅化步骤的半导体器件。 在其中半导体器件是MOSFET的优选实施例中，源极/漏极区域被硅化。 形成电介质层，并且从MOSFET的栅极电极去除蚀刻停止层。 执行第二硅化处理以对栅电极进行硅化。 可以针对每个晶体管单独执行该过程，从而允许单独确定每个晶体管的电特性。

公开(公告)号：US06872606B2

公开(公告)日：2005-03-29

申请号：US10406403

申请日：2003-04-03

申请人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/78618 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78684

摘要： A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.

摘要翻译： 具有凸起部分的装置及其制造方法。 提供SOI晶片，其具有衬底，设置在衬底上的绝缘层和设置在绝缘层上的半导体材料层。 图案化半导体材料以形成台面结构。 将晶片退火以在台面结构上形成凸起的段。

公开(公告)号：US06864519B2

公开(公告)日：2005-03-08

申请号：US10305728

申请日：2002-11-26

申请人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

发明人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

摘要： A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.

摘要翻译： 由一对P沟道多栅极场效应晶体管（P-MGFET），一对N沟道多栅极场效应晶体管（N）构成的互补金属氧化物半导体静态随机存取存储单元 -MGFET），第二对N-MGFET，其漏极分别连接到将第一对N-MGFET的N-MGFET的相应漏极连接到该对P-MGFET的漏极的连接 -MGFETs 一对互补位线，分别连接到第二对N-MGFETS的N-MGFET的源极; 以及连接到第二对N-MGFET的N-MGFET的门的字线。