公开(公告)号：US20070232078A1

公开(公告)日：2007-10-04

申请号：US11395853

申请日：2006-03-31

申请人： Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Robert S. Chau ,  Gilbert Dewey

发明人： Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Robert S. Chau ,  Gilbert Dewey

IPC分类号： H01L21/31

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7833

摘要： A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and patterning a gate electrode structure comprising the gate electrode material.

摘要翻译： 一种方法，包括在电介质材料上的衬底上沉积用于栅电极的材料，所述栅电极材料包括金属; 在不会促使与栅电极材料相关联的任何氧物质通过栅极电极材料移动到衬底的加工条件下，在栅电极材料上沉积封盖材料; 以及图案化包括栅电极材料的栅电极结构。

公开(公告)号：US07241653B2

公开(公告)日：2007-07-10

申请号：US11173443

申请日：2005-06-30

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US07226831B1

公开(公告)日：2007-06-05

申请号：US11320305

申请日：2005-12-27

申请人： Matthew V. Metz ,  Mark L. Doczy ,  Justin K. Brask ,  Robert S. Chau

发明人： Matthew V. Metz ,  Mark L. Doczy ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66636

摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.

摘要翻译： 本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。 在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

公开(公告)号：US07176090B2

公开(公告)日：2007-02-13

申请号：US10936114

申请日：2004-09-07

申请人： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L21/82385 ,  H01L21/28114 ,  H01L21/30608 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/66545 ,  Y10S438/926

摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成在第一层上并且比第一层更宽。 在除去牺牲结构以产生沟槽之后，在沟槽内形成金属栅电极。

公开(公告)号：US07170120B2

公开(公告)日：2007-01-30

申请号：US11096984

申请日：2005-03-31

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/76

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

公开(公告)号：US07126199B2

公开(公告)日：2006-10-24

申请号：US10951073

申请日：2004-09-27

申请人： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

发明人： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

IPC分类号： H01L29/94

CPC分类号： H01L21/823437 ,  H01L21/823828

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

摘要翻译： 互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。 可以在栅极电介质上方形成金属阻挡层。 在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

公开(公告)号：US07101761B2

公开(公告)日：2006-09-05

申请号：US10746323

申请日：2003-12-23

申请人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

发明人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  G11C2213/17 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/848

摘要： A method is described for providing a nanostructure suspended above a substrate surface. The method includes providing a nanostructure encased in an oxide shell on a substrate and depositing a sacrificial material and a support material over the oxide encased nanostructure. Then, the sacrificial material is removed to expose the oxide encased nanostructure. Once the oxide encased nanostructure has been exposed, the oxide shell is removed from the oxide encased nanostructure such that the nanostructure is suspended above the substrate surface.

摘要翻译： 描述了一种用于提供悬浮在衬底表面上方的纳米结构的方法。 该方法包括提供封装在衬底上的氧化物壳中的纳米结构，并在氧化物封装的纳米结构上沉积牺牲材料和载体材料。 然后，去除牺牲材料以暴露氧化物包裹的纳米结构。 一旦氧化物包裹的纳米结构已经暴露，氧化物壳被从氧化物封装的纳米结构中去除，使得纳米结构悬浮在衬底表面上方。

公开(公告)号：US07091129B2

公开(公告)日：2006-08-15

申请号：US10749347

申请日：2003-12-30

申请人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

发明人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

IPC分类号： H10L21/302 ,  H10L21/461 ,  H10L21/31 ,  H10L21/469

CPC分类号： C30B29/22 ,  C30B25/105 ,  C30B25/14 ,  C30B29/16

摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

公开(公告)号：US07078282B2

公开(公告)日：2006-07-18

申请号：US10749196

申请日：2003-12-30

申请人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

发明人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

公开(公告)号：US07074680B2

公开(公告)日：2006-07-11

申请号：US10935784

申请日：2004-09-07

申请人： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

发明人： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.