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1.发明授权Method of fabricating semiconductor devices with replacement, coaxial gate structure 有权用替代的同轴栅极结构制造半导体器件的方法公开(公告)号：US07101761B2
公开(公告)日：2006-09-05
申请号：US10746323
申请日：2003-12-23
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C2213/17 , H01L29/42384 , H01L29/66545 , H01L29/66772 , H01L29/785 , H01L29/78696 , H01L51/0048 , H01L51/0512 , Y10S977/848
摘要： A method is described for providing a nanostructure suspended above a substrate surface. The method includes providing a nanostructure encased in an oxide shell on a substrate and depositing a sacrificial material and a support material over the oxide encased nanostructure. Then, the sacrificial material is removed to expose the oxide encased nanostructure. Once the oxide encased nanostructure has been exposed, the oxide shell is removed from the oxide encased nanostructure such that the nanostructure is suspended above the substrate surface.
摘要翻译： 描述了一种用于提供悬浮在衬底表面上方的纳米结构的方法。 该方法包括提供封装在衬底上的氧化物壳中的纳米结构，并在氧化物封装的纳米结构上沉积牺牲材料和载体材料。 然后，去除牺牲材料以暴露氧化物包裹的纳米结构。 一旦氧化物包裹的纳米结构已经暴露，氧化物壳被从氧化物封装的纳米结构中去除，使得纳米结构悬浮在衬底表面上方。
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公开(公告)号：US07217611B2
公开(公告)日：2007-05-15
申请号：US10748383
申请日：2003-12-29
申请人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Scott A. Hareland , Matthew V. Metz , Chris E. Barns , Robert S. Chau
发明人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Scott A. Hareland , Matthew V. Metz , Chris E. Barns , Robert S. Chau
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/823842 , H01L29/495 , H01L29/66545 , Y10S438/926
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.
摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。
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3.发明授权公开(公告)号：US06939815B2
公开(公告)日：2005-09-06
申请号：US10652796
申请日：2003-08-28
申请人： Justin K. Brask , Mark L. Doczy , Scott A. Hareland , John P. Barnak , Matthew V. Metz , Jack Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Mark L. Doczy , Scott A. Hareland , John P. Barnak , Matthew V. Metz , Jack Kavalieros , Robert S. Chau
IPC分类号： H01L21/28 , H01L21/30 , H01L21/306 , H01L21/316 , H01L29/51 , H01L21/31
CPC分类号： H01L21/02244 , H01L21/02052 , H01L21/02337 , H01L21/0234 , H01L21/28167 , H01L21/28194 , H01L21/3003 , H01L21/31612 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31683 , H01L21/31691 , H01L29/513 , H01L29/517
摘要： A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.
摘要翻译： 描述制造半导体器件的方法。 该方法包括在基板上形成金属氧化物层，将金属氧化物层的至少一部分转化为金属层; 并氧化金属层以产生金属氧化物高k栅极电介质层。
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公开(公告)号：US07078282B2
公开(公告)日：2006-07-18
申请号：US10749196
申请日：2003-12-30
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/7842
摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.
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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号：US20120199813A1
公开(公告)日：2012-08-09
申请号：US13450359
申请日：2012-04-18
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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7.发明授权Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号：US07888221B2
公开(公告)日：2011-02-15
申请号：US12229459
申请日：2008-08-22
申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7391
摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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公开(公告)号：US07615441B2
公开(公告)日：2009-11-10
申请号：US11998236
申请日：2007-11-29
申请人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Gilbert Dewey , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L21/8242
CPC分类号： H01L21/0228 , H01L21/02052 , H01L21/02175 , H01L21/28167 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
摘要翻译： 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。
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9.发明申请Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress 审中-公开使用单轴压应力和双轴压应力的互补金属氧化物半导体集成电路公开(公告)号：US20090075445A1
公开(公告)日：2009-03-19
申请号：US12313368
申请日：2008-11-19
申请人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Brian S. Doyle , Robert S. Chau , Everett X. Wang , Philippe Matagne , Lucian Shifren , Been Y. Jin , Mark Stettler , Martin D. Giles
发明人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Brian S. Doyle , Robert S. Chau , Everett X. Wang , Philippe Matagne , Lucian Shifren , Been Y. Jin , Mark Stettler , Martin D. Giles
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41783 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/933
摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
摘要翻译： 晶体管可以由不同的硅锗层形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si1-xGex形式。 最高层可以是PMOS侧的Si1-yGey形式。 源极和漏极可以由PMOS侧的Si1-zGez形式的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在沟道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，这种压力的组合可能导致更高的移动性和增加的设备性能。
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10.发明申请Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode 有权制造具有高k栅极电介质层和金属栅电极的半导体器件的方法公开(公告)号：US20090042405A1
公开(公告)日：2009-02-12
申请号：US12157796
申请日：2008-06-12
申请人： Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Uday Shah , Matthew V. Metz , Suman Datta , Ramune Nagisetty , Robert S. Chau
发明人： Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Uday Shah , Matthew V. Metz , Suman Datta , Ramune Nagisetty , Robert S. Chau
IPC分类号： H01L21/469
CPC分类号： H01L21/823842
摘要： A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成第一电介质层，在第一介电层内形成沟槽，在衬底上形成第二电介质层。 第二电介质层具有形成在沟槽中的第一部分和第二部分。 在第二电介质层的第一和第二部分上形成具有第一功函数的第一金属层之后，第一金属层的一部分被转换成具有第二功函数的第二金属层。
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