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    Asynchronously resettable decoder for a semiconductor memory
    81.
    发明授权
    Asynchronously resettable decoder for a semiconductor memory 失效
    用于半导体存储器的异步复位解码器

    公开(公告)号：US06937538B2

    公开(公告)日：2005-08-30

    申请号：US09775477

    申请日：2001-02-02

    Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Mehdi Hatamian

    Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Mehdi Hatamian

    IPC: G11C7/06 ,  G11C8/10

    CPC classification number: G11C7/06

    Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n−1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

    Abstract translation: 具有存储器单元的分层存储器结构，以及与存储器单元耦合以形成第一层存储器模块的读出放大器和解码器，以及随后的层通过具有（n-1）层的存储器模块形成，所述存储器模块与（n） - 层读出放大器和（n）层译码器。 还提供了具有采样保持基准的单端读出放大器和电荷共享限制摆幅驱动读出放大器; 异步复位解码器; 具有行冗余性的字线解码器; 具有由冗余控制器操作的冗余存储单元的冗余设备; 扩散复制延迟电路; 高精度延迟测量电路; 以及在数据总线上施加有限的电压摆幅的数据传输总线电路。 提供了用于在没有插入的预充电周期的写后读取操作的方法，并且提供了具有插入的预充电周期的写后写入操作，任一操作在少于一个存储器访问周期中完成。

    Burn in system and method for improved memory reliability
    83.
    发明申请
    Burn in system and method for improved memory reliability 失效
    刻录系统和方法，提高内存可靠性

    公开(公告)号：US20050122805A1

    公开(公告)日：2005-06-09

    申请号：US11041829

    申请日：2005-01-24

    Applicant: Esin Terzioglu ,  Gil Winograd

    Inventor： Esin Terzioglu ,  Gil Winograd

    IPC: G11C29/50 ,  G11C7/00

    CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/2602

    Abstract: The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

    Abstract translation: 本发明涉及并行地应用分层存储器结构的系统和方法，测试弱缺陷的存储器结构。 本发明包括将逻辑0写入到存储器结构中的所有存储单元中。 所有高地址预编码线路和最低地址的交替预编码线路都被使能。 相邻字线和位线之间的电压降受到影响。 逻辑I被写入存储器结构中的所有存储器单元。 由于存储器单元中的逻辑1，在位线上产生相反的电压极性。 通过翻转最低预编码行的状态（即，通过改变对应于该行的输入地址），在字线上实现反向电压极性应力。

    Sense amplifier with adaptive reference generation
    84.
    发明授权
    Sense amplifier with adaptive reference generation 失效
    具有自适应参考产生的感应放大器

    公开(公告)号：US06901019B2

    公开(公告)日：2005-05-31

    申请号：US10853798

    申请日：2004-05-26

    Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

    Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

    IPC: G11C7/06 ,  G11C7/14 ,  G11C7/00

    CPC classification number: G11C7/065 ,  G11C7/14

    Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

    Abstract translation: 数字存储器系统（30）包括存储单元（52），位线（50），转移门（60），参考电压发生器（40），读出放大器（70）和控制电路（80）。 控制电路将位线预充电到采样和存储的位线预充电电压。 在位线隔离之后产生相应的参考电压。 位线和参考电压被耦合到读出放大器，使得基于存储在存储单元中的电荷接收电压。 然后，读出放大器与位线和参考电压隔离，并且读出放大器通电，从而从电荷和参考电压导出输出电压。

    Diffusion replica delay circuit method
    85.
    发明授权
    Diffusion replica delay circuit method 失效
    扩散复制延迟电路方法

    公开(公告)号：US06809971B2

    公开(公告)日：2004-10-26

    申请号：US10646317

    申请日：2003-08-22

    Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi

    Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi

    IPC: G11C700

    CPC classification number: G11C7/06

    Abstract: A method of implementing a diffusion replica delay circuit is provided in a device with a device capacitance and operational characteristics. A diffusion replica capacitor is coupled to the device and is capable of storing a predetermined replica charge representative of a selected device operational characteristic, and a diffusion replica transistor is coupled with the diffusion replica capacitor, and is coupled between the diffusion replica capacitor and a charge sink. The transistor is disposed to control the magnitude of the predetermined replica charge.

    High precision delay measurement circuit
    87.
    发明授权
    High precision delay measurement circuit 有权
    高精度延迟测量电路

    公开(公告)号：US06603712B2

    公开(公告)日：2003-08-05

    申请号：US09776262

    申请日：2001-02-02

    Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu

    Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu

    IPC: G04F1002

    CPC classification number: G11C7/06

    Abstract: A high-precision delay measurement circuit delivers exceptionally accurate time measurement, for example, a half-gate delay. The high-precision delay measurement circuit has a multi-stage ring oscillator coupled with multiple oscillation signal detectors, which can be counters and signal edge detection circuits, which respectively count the number of oscillations by the circuit, and determine the extent to which a particular oscillation signal propagated within the oscillator. Some oscillation counters, particularly those disposed between the stages of the oscillator are dual-edge detection counters. The high precision delay measurement circuit can have a control signal output which can constrain a limited voltage swing signal.

    Abstract translation: 高精度延迟测量电路提供非常精确的时间测量，例如半门延迟。 高精度延迟测量电路具有与多个振荡信号检测器耦合的多级环形振荡器，其可以是计数器和信号边缘检测电路，其分别计算电路的振荡次数，并确定特定的 振荡信号在振荡器内传播。 一些振荡计数器，特别是设置在振荡器级之间的振荡器是双边缘检测计数器。 高精度延迟测量电路可以具有可限制有限电压摆幅信号的控制信号输出。

    Circuit technique for high speed low power data transfer bus
    88.
    发明授权
    Circuit technique for high speed low power data transfer bus 失效
    高速低功耗数据传输总线的电路技术

    公开(公告)号：US06417697B2

    公开(公告)日：2002-07-09

    申请号：US09776028

    申请日：2001-02-02

    Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Mehdi Hatamian

    Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Mehdi Hatamian

    IPC: H03K190175

    CPC classification number: G11C7/06

    Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer. One preferred embodiment couples a first data bus and a second data bus with cross-linked inverters. Interposed between the inverters, and its associated bus, is a respective pMOS pass transistor. Also, coupled between each input node and ground, is a signal discharge transistor, preferably nMOS, which facilitates data transfer between the buses. Each of the inverters is coupled with a clocked charge/discharge circuit, preferably using a common clock signal.

    Abstract translation: 一种高速低功耗数据传输总线电路，通过在相关的数据总线上施加有限的受控电压摆幅来降低总线功耗。 在一个实施例中，反相器与pMOS传输晶体管和nMOS放电晶体管耦合，并且该组合与数据总线耦合。 放电晶体管和传输晶体管可以被编程以提供预选的总线操作特性。 在另一个实施例中，多个nMOS放电晶体管可以经由传输晶体管耦合到数据总线，其中每个放电晶体管被选择性地编程以提供附加的预选总线操作特性，多个可编程放电晶体管，因此可选地强加编码和多电平逻辑 信号在数据总线上。 在另一个实施例中，双向数据传输总线电路在传输期间施加有限的受控电压摆动来耦合两个数据总线。 一个优选实施例将第一数据总线和第二数据总线与交联逆变器相连。 反相器和其相关联的总线之间是相应的pMOS传输晶体管。 此外，耦合在每个输入节点和地之间的是信号放电晶体管，优选地是nMOS，其有利于总线之间的数据传输。 每个反相器与时钟充电/放电电路耦合，优选地使用公共时钟信号。

    Memory Configured to Provide Simultaneous Read/Write Access to Multiple Banks
    90.
    发明申请
    Memory Configured to Provide Simultaneous Read/Write Access to Multiple Banks 有权
    内存被配置为提供对多个银行的同时读/写访问

    公开(公告)号：US20130121086A1

    公开(公告)日：2013-05-16

    申请号：US13297771

    申请日：2011-11-16

    Applicant: Esin Terzioglu ,  Dongkyu Park

    Inventor： Esin Terzioglu ,  Dongkyu Park

    IPC: G11C7/10

    CPC classification number: G06F13/161 ,  G06F12/0855 ,  G06F12/0893 ,  G06F13/1663

    Abstract: A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is configured to receive first and second memory addresses and a first indication of an operation to be performed at the first memory addresses and a second indication of an operation to be performed at the second memory address and to instruct the first local controller to perform the first indicated operation at the first memory address and to instruct the second local controller to perform the second indicated operation at the second memory address at the same time.

    Abstract translation: 存储器包括至少第一和第二组单端口存储器元件，适于向第一存储体发送读取和写入指令的第一本地控制器，以及适于向第二存储器组发送读取和写入指令的第二本地控制器 。 全局控制器被配置为接收第一和第二存储器地址以及要在第一存储器地址处执行的操作的第一指示，以及要在第二存储器地址处执行的操作的第二指示，并且指示第一本地控制器 在第一存储器地址执行第一指示操作，并指示第二本地控制器同时在第二存储器地址处执行第二指示操作。

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