Centralizing the lock point of a synchronous circuit
    81.
    发明授权
    Centralizing the lock point of a synchronous circuit 失效
    集中同步电路的锁定点

    公开(公告)号:US07982519B2

    公开(公告)日:2011-07-19

    申请号:US12941749

    申请日:2010-11-08

    Applicant: Feng Lin

    Inventor: Feng Lin

    CPC classification number: H03L7/0814 H03L7/10

    Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

    Abstract translation: 公开了一种建立数字同步电路(例如,DLL)在其延迟线的中心或其中心附近的锁定点的系统和方法。 同步电路被配置为基于参考时钟的相位之间的选择性地使用参考时钟或其反相形式作为输入到延迟线的时钟信号,并且反相时钟可以在 确定相位关系。 对于延迟线的输入,选择性地使用参考时钟的相反阶段导致锁定点在大多数情况下的集中以及调谐范围的改善以及建立初始锁定的时间,而不需要额外的延迟 线。

    PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS
    82.
    发明申请
    PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS 失效
    使用数字延迟锁定的相位分离器

    公开(公告)号:US20110102036A1

    公开(公告)日:2011-05-05

    申请号:US12987431

    申请日:2011-01-10

    Abstract: A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

    Abstract translation: 分相器使用数字延迟锁定环(DLL)来接收互补输入时钟信号以产生具有不同相移的多个输出信号。 当DLL被锁定时,分相器的延迟分辨率等于DLL的两个延迟级。

    TRACKING AND OPTIMIZING GAIN AND CONTRAST IN REAL-TIME FOR ULTRASOUND IMAGING
    83.
    发明申请
    TRACKING AND OPTIMIZING GAIN AND CONTRAST IN REAL-TIME FOR ULTRASOUND IMAGING 审中-公开
    跟踪和优化实时增益和对比超声成像

    公开(公告)号:US20110054317A1

    公开(公告)日:2011-03-03

    申请号:US12551206

    申请日:2009-08-31

    Abstract: A system for dynamic optimization of gain and contrast in ultrasound imaging includes an image processor module programmed to dynamically estimate a correction profile in real-time and apply the correction profile to adjust a gain and contrast of image frame data sets. The image processor module is programmed to identify tissue and background regions in an image frame data set, determine an image intensity for each of the tissue and background regions, and formulate a gain profile based on the image intensity of the tissue region to compensate the gain variation of an image. The image processor module is further programmed to calculate an image contrast metric based on the image intensity of the tissue and background regions, and modify a gray map of the image frame data set based on the image contrast metric to adjust the contrast of an image displayed on the display system.

    Abstract translation: 用于超声成像中的增益和对比度的动态优化的系统包括被编程为实时动态地估计校正曲线的图像处理器模块,并应用校正轮廓来调整图像帧数据集的增益和对比度。 图像处理器模块被编程为识别图像帧数据集中的组织和背景区域,确定组织和背景区域中的每一个的图像强度,以及基于组织区域的图像强度来制定增益分布,以补偿增益 图像的变化。 图像处理器模块还被编程为基于组织和背景区域的图像强度来计算图像对比度量,并且基于图像对比度度量修改图像帧数据集的灰度图,以调整显示的图像的对比度 在显示系统上。

    Clock distribution network
    84.
    发明授权
    Clock distribution network 有权
    时钟分配网络

    公开(公告)号:US07888991B2

    公开(公告)日:2011-02-15

    申请号:US12408930

    申请日:2009-03-23

    Applicant: Feng Lin

    Inventor: Feng Lin

    CPC classification number: G06F1/10 H03K3/35613

    Abstract: Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.

    Abstract translation: 一些实施例包括具有基于电流模式逻辑(CML)和互补金属氧化物半导体(CMOS)组件的组合的时钟路径的装置和方法。

    Apparatus, system, and method for providing a continuous scanning sequence for ultrasound imaging
    85.
    发明授权
    Apparatus, system, and method for providing a continuous scanning sequence for ultrasound imaging 有权
    用于提供用于超声成像的连续扫描序列的装置,系统和方法

    公开(公告)号:US07846099B2

    公开(公告)日:2010-12-07

    申请号:US11551755

    申请日:2006-10-23

    CPC classification number: A61B8/00 A61B8/54

    Abstract: A method of performing a scanning sequence for an ultrasound scan includes establishing a number of ultrasound beams to be transmitted during an ultrasound scan, establishing a pulse repetition interval to be used for performing the ultrasound scan, and establishing a number of firings of each of the ultrasound beams to be performed during the ultrasound scan. The method further includes performing a scanning sequence based on a processing of one or more parameters selected from the group consisting of the number of ultrasound beams, the pulse repetition interval, and the number of firings of the ultrasound beams, wherein the processing of the one or more parameters is configured to provide a continuous interleaving in the transmitted beams thereby avoiding a generation of beam interleaving discontinuities and a formation of artifacts in a resulting image.

    Abstract translation: 执行超声扫描的扫描顺序的方法包括建立在超声扫描期间要发送的超声波束的数量,建立用于执行超声波扫描的脉冲重复间隔,以及建立多个发射 在超声扫描期间执行超声波束。 该方法还包括基于从由超声波束的数目,脉冲重复间隔和超声波束的发射次数组成的组中选择的一个或多个参数的处理来执行扫描序列,其中处理该一个 或更多的参数被配置为在所发送的波束中提供连续交织,从而避免波束交错不连续的产生以及在所得到的图像中的伪像的形成。

    SYSTEM AND METHOD FOR AUTOMATIC ULTRASOUND IMAGE OPTIMIZATION
    86.
    发明申请
    SYSTEM AND METHOD FOR AUTOMATIC ULTRASOUND IMAGE OPTIMIZATION 有权
    自动超声波图像优化的系统与方法

    公开(公告)号:US20100305441A1

    公开(公告)日:2010-12-02

    申请号:US12471732

    申请日:2009-05-26

    CPC classification number: A61B8/00 A61B8/14 G01S7/52046 G01S7/5205

    Abstract: A method for automatic image optimization in ultrasound imaging of an object is provided. The method includes transmitting a first ultrasound signal into the object, wherein the signal has a plurality of first signal parameters. The method also includes receiving a first set of electrical signals representing reflections of the first ultrasound signals from the object and processing the first set of electrical signals into a first image. The method evaluates an image quality cost function for the first image to produce a first image quality metric and determines a second plurality of signal parameters based upon the first image quality metric. Similarly, the method includes transmitting a second ultrasound signal into the object, wherein the signal has the second plurality of signal parameters and receiving a second set of electrical signals representing reflections of the second ultrasound signal from the object and processing the second set of electrical signals into a second image. The method also includes evaluating an image quality cost function for the second image to produce a second image quality metric. The method further includes comparing the first image quality metric and the second image quality metric to determine whether a maximized image quality metric has been reached and assigning multiple signal parameters that produced the maximized image quality metric as optimum parameters. The method further includes imaging and displaying the object using an ultrasound signal having the optimum parameters.

    Abstract translation: 提供了一种用于物体超声成像自动图像优化的方法。 该方法包括将第一超声信号发送到对象中,其中该信号具有多个第一信号参数。 该方法还包括接收表示来自对象的第一超声信号的反射的第一组电信号,并将第一组电信号处理成第一图像。 该方法评估第一图像的图像质量成本函数以产生第一图像质量度量,并且基于第一图像质量度量确定第二多个信号参数。 类似地,该方法包括将第二超声信号发送到对象中,其中信号具有第二多个信号参数,并且接收表示来自对象的第二超声信号的反射的第二组电信号,并处理第二组电信号 进入第二个图像。 该方法还包括评估第二图像的图像质量成本函数以产生第二图像质量度量。 该方法还包括比较第一图像质量度量和第二图像质量度量,以确定是否已经达到最大化图像质量度量,并且分配产生最大化图像质量度量的多个信号参数作为最佳参数。 该方法还包括使用具有最佳参数的超声信号对物体进行成像和显示。

    Method for improving stability and lock time for synchronous circuits
    87.
    发明授权
    Method for improving stability and lock time for synchronous circuits 有权
    提高同步电路稳定性和锁定时间的方法

    公开(公告)号:US07812593B2

    公开(公告)日:2010-10-12

    申请号:US12202685

    申请日:2008-09-02

    Abstract: Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward loop path and the feedback loop path. The phase detector is coupled to both the forward and feedback loop path circuits and is configured to periodically adjust responsive to a calculated loop delay of the test clock signal. The phase detector is thereafter able to stabilize at an improved rate.

    Abstract translation: 描述了延迟锁定环路,信号锁定方法和包含延迟锁定环路的设备。 延迟锁定环路包括正向环路径,反馈环路径和相位检测器。 临时切换测试时钟信号以遍历正向环路径和反馈环路径。 相位检测器耦合到正向和反馈环路径电路两者,并且被配置为响应于所计算的测试时钟信号的环路延迟而周期性地调整。 此后,相位检测器能够以更高的速率稳定。

    RF circuit with stacked printed circuit boards
    89.
    发明授权
    RF circuit with stacked printed circuit boards 有权
    RF电路与堆叠的印刷电路板

    公开(公告)号:US07725095B2

    公开(公告)日:2010-05-25

    申请号:US10586292

    申请日:2004-11-04

    CPC classification number: H05K7/1417 H05K1/144 H05K9/002

    Abstract: An RF unit comprises a tuner, a demodulator and a mixer. At least the tuner and the mixer are disposed on separate first and second substrates. The RF unit further comprises a housing accommodating the first and second substrates. The first substrate and the second substrate are arranged on different levels inside the housing and maintain a predetermined distance between each other.

    Abstract translation: RF单元包括调谐器,解调器和混频器。 至少调谐器和混合器设置在分开的第一和第二基板上。 RF单元还包括容纳第一和第二基板的壳体。 第一基板和第二基板布置在壳体内的不同水平面上并保持彼此之间的预定距离。

    Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal
    90.
    发明授权
    Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal 有权
    使用双边相位检测的占空比校正的多相发生器和用于产生多相信号的方法

    公开(公告)号:US07724049B2

    公开(公告)日:2010-05-25

    申请号:US11712162

    申请日:2007-02-28

    CPC classification number: G06F1/10 H03K5/133 H03L7/0805 H03L7/0812 H03L7/085

    Abstract: Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.

    Abstract translation: 这里通常描述具有占空比校正的多相发生器的实施例。 在一些实施例中,多相发生器包括串联布置的可控延迟级和双边缘相位检测器电路。 双边缘相位检测器电路可以产生控制信号,以基于由延迟级操作的相同状态信号的相应上升沿和相应的下降沿来调整由延迟级提供的延迟。 描述其他电路,系统和方法。

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