Abstract:
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.
Abstract:
A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.
Abstract:
A system for dynamic optimization of gain and contrast in ultrasound imaging includes an image processor module programmed to dynamically estimate a correction profile in real-time and apply the correction profile to adjust a gain and contrast of image frame data sets. The image processor module is programmed to identify tissue and background regions in an image frame data set, determine an image intensity for each of the tissue and background regions, and formulate a gain profile based on the image intensity of the tissue region to compensate the gain variation of an image. The image processor module is further programmed to calculate an image contrast metric based on the image intensity of the tissue and background regions, and modify a gray map of the image frame data set based on the image contrast metric to adjust the contrast of an image displayed on the display system.
Abstract:
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.
Abstract:
A method of performing a scanning sequence for an ultrasound scan includes establishing a number of ultrasound beams to be transmitted during an ultrasound scan, establishing a pulse repetition interval to be used for performing the ultrasound scan, and establishing a number of firings of each of the ultrasound beams to be performed during the ultrasound scan. The method further includes performing a scanning sequence based on a processing of one or more parameters selected from the group consisting of the number of ultrasound beams, the pulse repetition interval, and the number of firings of the ultrasound beams, wherein the processing of the one or more parameters is configured to provide a continuous interleaving in the transmitted beams thereby avoiding a generation of beam interleaving discontinuities and a formation of artifacts in a resulting image.
Abstract:
A method for automatic image optimization in ultrasound imaging of an object is provided. The method includes transmitting a first ultrasound signal into the object, wherein the signal has a plurality of first signal parameters. The method also includes receiving a first set of electrical signals representing reflections of the first ultrasound signals from the object and processing the first set of electrical signals into a first image. The method evaluates an image quality cost function for the first image to produce a first image quality metric and determines a second plurality of signal parameters based upon the first image quality metric. Similarly, the method includes transmitting a second ultrasound signal into the object, wherein the signal has the second plurality of signal parameters and receiving a second set of electrical signals representing reflections of the second ultrasound signal from the object and processing the second set of electrical signals into a second image. The method also includes evaluating an image quality cost function for the second image to produce a second image quality metric. The method further includes comparing the first image quality metric and the second image quality metric to determine whether a maximized image quality metric has been reached and assigning multiple signal parameters that produced the maximized image quality metric as optimum parameters. The method further includes imaging and displaying the object using an ultrasound signal having the optimum parameters.
Abstract:
Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward loop path and the feedback loop path. The phase detector is coupled to both the forward and feedback loop path circuits and is configured to periodically adjust responsive to a calculated loop delay of the test clock signal. The phase detector is thereafter able to stabilize at an improved rate.
Abstract:
An ultrasound imaging method is provided. The method includes identifying a plurality of locations within a region of interest, delivering a pulse sequence to two or more of the plurality of locations in a determined order, wherein the pulse sequence comprises a pushing pulse, and a tracking pulse, and applying a motion correction sequence to each of the plurality of locations where the pulse sequence is delivered.
Abstract:
An RF unit comprises a tuner, a demodulator and a mixer. At least the tuner and the mixer are disposed on separate first and second substrates. The RF unit further comprises a housing accommodating the first and second substrates. The first substrate and the second substrate are arranged on different levels inside the housing and maintain a predetermined distance between each other.
Abstract:
Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.