公开(公告)号：US20060091428A1

公开(公告)日：2006-05-04

申请号：US11300896

申请日：2005-12-15

申请人： Yee-Chia Yeo ,  Fu-Liang Yang

发明人： Yee-Chia Yeo ,  Fu-Liang Yang

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over the first gate electrode material. The second gate electrode material is planarized and then etched selectively with respect to first gate electrode material. The first gate electrode material can then be etched.

摘要翻译： 在形成半导体器件的方法中，半导体鳍片形成在绝缘体上半导体衬底上。 在半导体鳍片的至少一部分上形成栅极电介质。 第一栅极电极材料形成在栅极电介质上，并且第二栅电极材料形成在第一栅电极材料上。 平面化第二栅电极材料，然后相对于第一栅电极材料选择性地蚀刻。 然后可以蚀刻第一栅电极材料。

公开(公告)号：US06835967B2

公开(公告)日：2004-12-28

申请号：US10400002

申请日：2003-03-25

申请人： Yee-Chia Yeo ,  Fu-Liang Yang

发明人： Yee-Chia Yeo ,  Fu-Liang Yang

IPC分类号： H01L29885

CPC分类号： H01L29/88 ,  H01L27/0255 ,  H01L27/0814 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting the second heavily-doped region.

公开(公告)号：US07208815B2

公开(公告)日：2007-04-24

申请号：US10989080

申请日：2004-11-15

申请人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842 ,  H01L29/785

摘要： In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

摘要翻译： 在本发明的优选实施例中，描述了使用SOI和混合衬底取向形成CMOS器件的方法。 根据优选实施例，衬底可以具有多个晶体取向。 衬底中的一个逻辑门可以包括在一个晶体取向上的至少一个N-FET和另一个晶体取向上的至少一个P-FET。 衬底中的另一个逻辑门可以包括至少一个N-FET和至少一个相同取向的P-FET。 替代实施例还包括确定基板的优选解理平面并且考虑到它们各自优选的解理平面使基板相对于彼此定向。 在优选实施例中，解理平面不平行。

公开(公告)号：US06674130B2

公开(公告)日：2004-01-06

申请号：US10316601

申请日：2002-12-11

申请人： Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L2362

CPC分类号： H01L29/4983 ,  H01L29/0895 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78612 ,  H01L2924/0002 ,  Y10S438/979 ,  H01L2924/00

摘要： A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

摘要翻译： 描述了一种新型的部分耗尽的SOI MOSFET，其中引入了栅极和基极之间的隧道连接。 这通过使用其厚度低于其隧道阈值的栅极电介质实现。 栅极基座比正常长一些，一端附近的区域植入P +（或PMOS器件中的N +）。 这允许空穴（PMOS的电子）从栅极到基极隧道。 由于空穴电流是自限制的，所以可以使用大于0.7伏的施加电压，而不会引起过大的泄漏（如现有技术的DTMOS器件的情况）。 还描述了用于制造该装置的方法。

公开(公告)号：US07342289B2

公开(公告)日：2008-03-11

申请号：US10637351

申请日：2003-08-08

申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US20070228372A1

公开(公告)日：2007-10-04

申请号：US11761547

申请日：2007-06-12

申请人： Kuo-Nan Yang ,  Yi-Lang Chen ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Kuo-Nan Yang ,  Yi-Lang Chen ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/58

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78615

摘要： A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.

摘要翻译： 提供了一种用于制造具有主体触点的Finfet器件的方法和使用该方法制造的器件。 在一个示例中，提供绝缘体上硅衬底。 在绝缘体上硅衬底的硅层中限定T形有源区。 源极区域和漏极区域形成T形有源区域的横杆的两个端部，并且主体接触区域形成T形有源区域的腿部。 在有源区上生长栅氧化层。 沉积覆盖栅极氧化物层的多晶硅层并图案化以形成栅极，其中栅极的一端部分覆盖在主体接触区域上，以完成具有身体接触的Finfet器件的形成。

公开(公告)号：US07183137B2

公开(公告)日：2007-02-27

申请号：US10725697

申请日：2003-12-01

申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/50 ,  H01L21/78

CPC分类号： H01L21/78 ,  B28D5/00

摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.

摘要翻译： 公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

公开(公告)号：US20050253193A1

公开(公告)日：2005-11-17

申请号：US10835789

申请日：2004-04-30

申请人： Haur-Ywh Chen ,  Fang-Cheng Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Haur-Ywh Chen ,  Fang-Cheng Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/665 ,  H01L29/66795

摘要： A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

摘要翻译： 一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在 器件结构，已经开发。 通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。 制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。 在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。 金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

公开(公告)号：US08288842B2

公开(公告)日：2012-10-16

申请号：US11655008

申请日：2007-01-18

申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/544 ,  H01L21/301

CPC分类号： H01L21/78 ,  B28D5/00

摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

公开(公告)号：US07187000B2

公开(公告)日：2007-03-06

申请号：US11081993

申请日：2005-03-16

申请人： Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/62 ,  H01L29/10

CPC分类号： H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.

摘要翻译： 提供半导体结构及其制造方法。 在一个示例中，该结构包括掺杂有第一类型掺杂剂的阱区（例如，P型或N型掺杂剂）。 形成在阱区上方的栅极基座具有两个端部，其中一个端部至少部分地覆盖阱区域并且掺杂有第一类型的掺杂剂。 电介质层位于门基座和阱区之间。 形成在阱区内的栅极基座的相对侧上的源极和漏极区域掺杂有与第一类型掺杂物类型相反的第二类型掺杂物。