公开(公告)号：US09412736B2

公开(公告)日：2016-08-09

申请号：US14296812

申请日：2014-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Ding ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Robert M. Rassel ,  Sebastian T. Ventrone

IPC: H01L21/30 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0694 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Abstract translation: 在制造绝缘体上硅晶片的方法中，注入一个或多个半导体器件元件，并且在第一半导体晶片的顶表面上形成一个或多个浅沟槽隔离。 在第一半导体晶片的顶表面上沉积第一介电材料层，填充浅沟槽隔离物。 在第二半导体晶片的底面上的电介质材料层与第一半导体晶片的顶部的电介质材料层接合，在第二半导体晶片的顶面上形成有一个以上的半导体装置。 然后，产生连接第二半导体晶片的顶表面上的一个或多个半导体器件和第一半导体晶片的顶表面上的一个或多个半导体器件元件的一个或多个穿过硅通孔。

公开(公告)号：US20160163685A1

公开(公告)日：2016-06-09

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以围绕器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。

公开(公告)号：US09299590B1

公开(公告)日：2016-03-29

申请号：US14743030

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Ezra D. B. Hall ,  Vibhor Jain ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC: H01L21/66 ,  H01L21/48 ,  H01L21/78 ,  H01L21/768 ,  H01L21/56 ,  H01L23/38 ,  H01L23/367

CPC classification number: H01L23/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

Abstract translation: 各种具体实施例包括形成集成电路（IC）装置的方法，包括：基于IC器件中的升高温度区域的已知位置，在处理晶片的上表面上形成至少一个热电冷却装置; 在覆盖所述热电冷却装置的所述处理晶片上形成第一氧化物层; 在供体硅晶片上形成第二氧化物层以形成施主晶片; 在第一氧化物层和第二氧化物层处将施主晶片接合到处理晶片，使得第二氧化物层接触处理晶片上的第一氧化物层; 以及在施主晶片的供体硅晶片侧上形成至少一个半导体器件，其中所述至少一个热电冷却器件位于所述至少一个半导体器件附近。

公开(公告)号：US09245951B1

公开(公告)日：2016-01-26

申请号：US14487582

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0826 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7378

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在衬底的顶表面上形成一层。 在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。 在沟槽中形成双极结型晶体管的集电极基座。