公开(公告)号：US08120838B2

公开(公告)日：2012-02-21

申请号：US12783170

申请日：2010-05-19

Applicant: Hsiang-Lin Lin ,  Wei-Ming Huang ,  Chih-Jen Hu

Inventor： Hsiang-Lin Lin ,  Wei-Ming Huang ,  Chih-Jen Hu

IPC: G02B26/00 ,  G09G3/34

CPC classification number: G09G3/3446 ,  G02F1/167 ,  G02F2001/1676 ,  G09G2300/0434

Abstract: The present invention in one aspect relates to a solar cell formed on a substrate, a bottom electrode member formed on the solar cell, an electrophoretic display panel formed on the bottom electrode member, having a plurality of electrophoretic cell structures spatially arranged in a matrix form, each electrophoretic cell structure containing a plurality of charged particles movable in the electrophoretic cell structure responsively to applied fields, and a top electrode member formed on the electrophoretic display panel, where at least one of the bottom electrode member and the top electrode member includes a plurality of in-plane switching (IPS) electrodes. Each IPS electrode is positioned in relation to a corresponding electrophoretic cell structure for controlling movements of the charged particles therein along a horizontal direction parallel to the electrophoretic display panel.

Abstract translation: 本发明一方面涉及形成在基板上的太阳能电池，形成在太阳能电池上的底部电极部件，形成在底部电极部件上的电泳显示面板，具有以矩阵形式空间排列的多个电泳单元结构体 每个电泳单元结构包含响应于施加场的可在电泳单元结构中移动的多个带电粒子，以及形成在电泳显示面板上的顶电极构件，其中底电极构件和顶电极构件中的至少一个包括 多个平面内切换（IPS）电极。 每个IPS电极相对于相应的电泳池结构定位，用于沿着平行于电泳显示面板的水平方向控制带电粒子在其中的移动。

公开(公告)号：US08071407B2

公开(公告)日：2011-12-06

申请号：US12835874

申请日：2010-07-14

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化 半导体层和图案化金属多层。 此外，本发明使用选择性蚀刻某些层的方法。 使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少与制造阵列基板有关的耗时且复杂的掩模蚀刻工艺的数量。 本发明提供了用于制造阵列基板的相对简单且省时的方法。

公开(公告)号：US20110292327A1

公开(公告)日：2011-12-01

申请号：US13136511

申请日：2011-08-02

Applicant: Hsiang-Lin Lin ,  Chun-Chieh Tsao

Inventor： Hsiang-Lin Lin ,  Chun-Chieh Tsao

IPC: G02F1/1335

CPC classification number: G03F7/40 ,  G02F1/133504 ,  G02F1/133555 ,  G02F2201/123 ,  G03F7/0007 ,  H01R13/6675 ,  H02J7/0068 ,  Y10T307/625 ,  Y10T428/1068

Abstract: A method for producing a light reflecting structure in a transflective or reflective liquid crystal display uses one or two masks for masking a photoresist layer in a back-side exposing process. The pattern on the masks is designed to produce rod-like structures or crevices and holes on exposed and developed photoresist layer. After the exposed photoresist is developed, a heat treatment process or a UV curing process is used to soften the photoresist layer so that the reshaped surface is more or less contiguous but uneven. A reflective coating is then deposited on the uneven surface. One or more intermediate layers can be made between the masks, between the lower mask and the substrate, and between the upper masks and the photoresist layers. The masks and the intermediate layers can be made in conjunction with the fabrication of the liquid crystal display panel.

Abstract translation: 在半反射或反射型液晶显示器中制造光反射结构的方法使用一个或两个掩模来掩模背面曝光工艺中的光致抗蚀剂层。 掩模上的图案被设计成在曝光和显影的光致抗蚀剂层上产生棒状结构或缝隙和孔。 曝光的光致抗蚀剂显影后，使用热处理工艺或UV固化工艺来软化光致抗蚀剂层，使得整形表面或多或少地连续但不均匀。 然后将反射涂层沉积在不平坦表面上。 可以在掩模之间，下掩模和基板之间以及上掩模和光致抗蚀剂层之间形成一个或多个中间层。 掩模和中间层可以与液晶显示面板的制造相结合。

公开(公告)号：US20110286076A1

公开(公告)日：2011-11-24

申请号：US12783170

申请日：2010-05-19

Applicant: Hsiang-Lin Lin ,  Wei-Ming Huang ,  Chih-Jen Hu

Inventor： Hsiang-Lin Lin ,  Wei-Ming Huang ,  Chih-Jen Hu

IPC: G02F1/167

CPC classification number: G09G3/3446 ,  G02F1/167 ,  G02F2001/1676 ,  G09G2300/0434

Abstract: The present invention in one aspect relates to a solar cell formed on a substrate, a bottom electrode member formed on the solar cell, an electrophoretic display panel formed on the bottom electrode member, having a plurality of electrophoretic cell structures spatially arranged in a matrix form, each electrophoretic cell structure containing a plurality of charged particles movable in the electrophoretic cell structure responsively to applied fields, and a top electrode member formed on the electrophoretic display panel, where at least one of the bottom electrode member and the top electrode member includes a plurality of in-plane switching (IPS) electrodes. Each IPS electrode is positioned in relation to a corresponding electrophoretic cell structure for controlling movements of the charged particles therein along a horizontal direction parallel to the electrophoretic display panel.

Abstract translation: 本发明一方面涉及形成在基板上的太阳能电池，形成在太阳能电池上的底部电极部件，形成在底部电极部件上的电泳显示面板，具有以矩阵形式空间排列的多个电泳单元结构体 每个电泳单元结构包含响应于施加场的可在电泳单元结构中移动的多个带电粒子，以及形成在电泳显示面板上的顶电极构件，其中底电极构件和顶电极构件中的至少一个包括 多个平面内切换（IPS）电极。 每个IPS电极相对于相应的电泳池结构定位，用于沿着平行于电泳显示面板的水平方向控制带电粒子在其中的移动。

公开(公告)号：US20110244615A1

公开(公告)日：2011-10-06

申请号：US13163774

申请日：2011-06-20

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

IPC: H01L21/70

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1288

Abstract: A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.

Abstract translation: 像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。 数据线包括第一数据金属段和第二数据金属层。 有源元件包括栅电极，绝缘层，沟道层，源极和漏极。 沟道层位于栅电极上方的绝缘层上。 源极和漏极位于沟道层上。 源耦合到数据线。 第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。 第二钝化层覆盖漏极的一部分边缘。 像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。

公开(公告)号：US20110216256A1

公开(公告)日：2011-09-08

申请号：US12781805

申请日：2010-05-17

Applicant: Hsiang-Lin Lin ,  An-Thung Cho ,  Chih-Jen Hu ,  Wei-Ming Huang

Inventor： Hsiang-Lin Lin ,  An-Thung Cho ,  Chih-Jen Hu ,  Wei-Ming Huang

IPC: G02F1/135 ,  H01J9/24

CPC classification number: G02F1/135 ,  H01J9/24

Abstract: A reflective type touch-sensing display panel including a front substrate, scan lines, data lines, pixel structures, photo-sensors, readout devices, a rear substrate and a reflective display medium is provided. The front substrate has an inner surface. The scan lines and the data lines are on the inner surface of the front substrate and intersected to each other. The pixel structures are disposed on the inner surface of the front substrate, and each pixel structure is electrically connected to one of the scan lines and one of the data lines correspondingly. The photo-sensors are disposed on the inner surface of the front substrate. Each readout device is electrically connected to one of the photo-sensor correspondingly. The rear substrate is disposed opposite to the front substrate. The reflective display medium is sealed between the front substrate and the rear substrate.

Abstract translation: 提供了包括前基板，扫描线，数据线，像素结构，光传感器，读出装置，后基板和反射显示介质的反射型触摸感测显示面板。 前基板具有内表面。 扫描线和数据线位于前基板的内表面上并彼此相交。 像素结构设置在前基板的内表面上，并且每个像素结构相应地电连接到扫描线之一和数据线之一。 光传感器设置在前基板的内表面上。 每个读出装置相应地电连接到一个光电传感器。 后基板与前基板相对设置。 反射显示介质被密封在前基板和后基板之间。

公开(公告)号：US20100279450A1

公开(公告)日：2010-11-04

申请号：US12835874

申请日：2010-07-14

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化 半导体层和图案化金属多层。 此外，本发明使用选择性蚀刻某些层的方法。 使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。 本发明提供了用于制造阵列基板的相对简单且省时的方法。

公开(公告)号：US07808567B2

公开(公告)日：2010-10-05

申请号：US11941534

申请日：2007-11-16

Applicant: Hsiang-Lin Lin ,  Seok-Lyul Lee ,  Tun-Chun Yang

Inventor： Hsiang-Lin Lin ,  Seok-Lyul Lee ,  Tun-Chun Yang

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/139

CPC classification number: G02F1/133707 ,  G02F1/134336 ,  G02F2201/40 ,  H01L27/124 ,  H01L29/42384

Abstract: A pixel structure is provided. The pixel structure comprises a lower substrate with a transistor and pixel area; a first patterned conductive layer, which has a data line and a gate within the transistor area that is disposed on the lower substrate; a patterned insulator layer covering the first patterned conductive layer; an active layer disposed on the patterned insulator layer above the gate; a second patterned conductive layer with a gate line disposed on the patterned insulator layer, source and drain, wherein the source and the drain are disposed on the active layer; a pixel electrode disposed on the patterned insulator layer and electrically connected to the drain; a patterned passivation layer disposed on the patterned insulator layer, gate line, source, drain and pixel electrode; and a third patterned conductive layer, which has a data line connecting electrode, a gate line connecting electrode, at least one alignment electrode and a common electrode. The data line is electrically connected to the source through the data line connecting electrode; the gate line is electrically connected to the gate through the gate line connecting electrode; the alignment electrode is electrically connected to the pixel electrode; and a portion of the common electrode is disposed above the data line.

Abstract translation: 提供像素结构。 像素结构包括具有晶体管和像素区域的下基板; 第一图案化导电层，其具有设置在下基板上的晶体管区域内的数据线和栅极; 覆盖所述第一图案化导电层的图案化绝缘体层; 设置在栅极上方的图案化绝缘体层上的有源层; 第二图案化导电层，其栅极线设置在图案化绝缘体层，源极和漏极上，其中源极和漏极设置在有源层上; 设置在所述图案化绝缘体层上并电连接到所述漏极的像素电极; 布置在图案化绝缘体层，栅极线，源极，漏极和像素电极上的图案化钝化层; 以及具有数据线连接电极，栅极线连接电极，至少一个取向电极和公共电极的第三图案化导电层。 数据线通过数据线连接电极与源极电连接; 栅极线通过栅极线连接电极电连接到栅极; 对准电极电连接到像素电极; 并且公共电极的一部分设置在数据线的上方。

公开(公告)号：US07754547B2

公开(公告)日：2010-07-13

申请号：US12102027

申请日：2008-04-14

Applicant: Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

Inventor： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC: H01L21/00

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract translation: 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US07687289B2

公开(公告)日：2010-03-30

申请号：US11863283

申请日：2007-09-28

Applicant: Hsiang-Lin Lin ,  Sung-Kao Liu

Inventor： Hsiang-Lin Lin ,  Sung-Kao Liu

IPC: H01L21/00

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2001/136218

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract translation: 提供了一种制造像素结构的方法。 在基板上形成包括栅极和数据线的第一图案化导电层。 形成栅极绝缘层以覆盖第一图案化导电层，并且在栅极上方的栅极绝缘层上形成半导体沟道层。 包括扫描线，公共线，源极和漏极的第二图案化导电层形成在栅极绝缘层和半导体沟道层上。 扫描线连接到栅极，公共线位于数据线上方。 源极和漏极位于半导体沟道层上，源极连接到数据线。 在衬底上形成钝化层以覆盖第二图案化导电层。 连接到漏极的像素电极形成在钝化层上。