公开(公告)号：US11107444B2

公开(公告)日：2021-08-31

申请号：US16723337

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G09G5/377 ,  G06F3/14

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US10957096B2

公开(公告)日：2021-03-23

申请号：US16447397

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US10937126B2

公开(公告)日：2021-03-02

申请号：US15982680

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T3/40 ,  G06T1/20

Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.

公开(公告)号：US20200293282A1

公开(公告)日：2020-09-17

申请号：US16833128

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： YANIV Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200073810A1

公开(公告)日：2020-03-05

申请号：US16566188

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38 ,  G06F12/0855 ,  G06F12/0811

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US10467795B2

公开(公告)日：2019-11-05

申请号：US15482724

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/02 ,  G06T15/00 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US10223773B2

公开(公告)日：2019-03-05

申请号：US15477003

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06T5/00 ,  G06T1/20 ,  G06T15/00 ,  G06T15/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20180314492A1

公开(公告)日：2018-11-01

申请号：US15499893

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N99/00

CPC classification number: G06F7/5332 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293787A1

公开(公告)日：2018-10-11

申请号：US15483409

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/80 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20180293758A1

公开(公告)日：2018-10-11

申请号：US15482725

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.