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    EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION
    81.
    发明申请
    EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION 有权
    在错误检测完成前的早期数据传送

    公开(公告)号：US20140281751A1

    公开(公告)日：2014-09-18

    申请号：US13834959

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Glenn D. Gilda ,  Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC: G06F11/07

    CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

    Abstract: Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.

    Abstract translation: 实施例涉及在存储器系统中的错误检测完成之前的早期数据传送。 一个方面是包括具有系统域中的校正流水线的缓存子系统接口的系统。 该系统包括存储器控制器嵌套域中的存储器控​​制单元接口和在系统域和存储器控制器嵌套域之间提供异步边界层的缓冲器控制块。 控制器被配置为接收多帧数据块的帧并将该帧写入缓冲器控制块。 在完成多帧数据块的错误检测之前，该帧由高速缓存子系统接口读取。 对存储器控制器嵌套域中的帧执行错误检测。 基于检测到帧中的错误，拦截信号从存储器控制器嵌套域发送到系统域中的校正流水线。

    DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM
    82.
    发明申请
    DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM 有权
    双重异步和同步记忆系统

    公开(公告)号：US20140281326A1

    公开(公告)日：2014-09-18

    申请号：US13835521

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

    IPC: G11C7/22

    CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

    Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

    Abstract translation: 实施例涉及双异步和同步存储器系统。 一个方面是一种系统，其包括存储器控制器和经由同步信道耦合到存储器控制器的存储器缓冲器芯片。 存储器缓冲器芯片包括被配置为与嵌套域中的存储器控​​制器同步通信的存储器缓冲器单元和被配置为与存储器域中的至少一个存储器接口端口通信的存储器缓冲适配器。 所述至少一个存储器接口端口可操作以访问至少一个存储器设备。 边界层连接到嵌套域和存储域，其中边界层可配置为在嵌套和存储器域之间以同步传输模式操作并且在嵌套和存储器域之间以异步传输模式操作。

    ADDRESS MAPPING INCLUDING GENERIC BITS
    83.
    发明申请
    ADDRESS MAPPING INCLUDING GENERIC BITS 有权
    地址映射，包括通用位

    公开(公告)号：US20140281191A1

    公开(公告)日：2014-09-18

    申请号：US13835259

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Eric E. Retter ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Glenn D. Gilda ,  Mark R. Hodges

    IPC: G11C7/10

    CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F13/16 ,  G06F13/1694 ,  G06F13/4243 ,  G11C8/06

    Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

    Abstract translation: 实施例涉及包括通用位的地址映射。 一个方面包括通过主存储器中的缓冲器模块从存储器控制单元（MCU）接收包括通用位的地址。 另一方面包括将通用位映射到与由缓冲器模块与缓冲器模块相关联的存储器子系统中的动态随机存取存储器（DRAM）类型对应的地址格式。 另一方面包括基于所映射的通用位，通过缓冲器模块访问存储器子系统中的DRAM中的物理位置。

    First-in-first-out queue-based command spreading
    84.
    发明授权
    First-in-first-out queue-based command spreading 有权
    先进先出的基于队列的命令传播

    公开(公告)号：US08832324B1

    公开(公告)日：2014-09-09

    申请号：US13835205

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC: G06F13/368 ,  G06F13/18 ,  G06F3/06

    CPC classification number: G06F13/1642 ,  Y02D10/14

    Abstract: Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage. Another aspect includes a third level priority on the buffer chip associated with each respective FIFO queue to help optimize the bandwidth on the returning upstream fetch bus.

    Abstract translation: 实施例涉及先进先出（FIFO）队列的命令扩展。 一个方面包括通过存储器控制单元（MCU）的第一级优先级接收多个命令，其中多个命令中的每一个与位于缓冲器芯片上的多个端口中的一个相关联。 另一方面包括将多个命令中的每一个存储在MCU中的多个FIFO队列的FIFO队列中，其中多个命令中的每一个基于命令的相关端口被分配给FIFO队列，并且多个 FIFO队列与位于缓冲器芯片上的多个端口中的相应一个端口相关联。 另一方面包括选择多个FIFO队列中的FIFO队列，并通过第二级优先级将来自所选FIFO队列的命令转发到缓冲器芯片。 另一方面包括与每个相应FIFO队列相关联的缓冲器芯片的第三级优先级，以帮助优化返回的上行获取总线上的带宽。

    SYSTEM AND METHOD TO INJECT A BIT ERROR ON A BUS LANE
    85.
    发明申请
    SYSTEM AND METHOD TO INJECT A BIT ERROR ON A BUS LANE 有权
    在总线上引入位错误的系统和方法

    公开(公告)号：US20140173361A1

    公开(公告)日：2014-06-19

    申请号：US13714531

    申请日：2012-12-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Patrick J. Meaney ,  Michael B. Spear ,  Kenneth L. Wright

    IPC: G06F11/00

    CPC classification number: G06F11/004 ,  G06F11/221 ,  G06F11/25

    Abstract: A method includes modifying, at a bit error injection circuit, a multiplier value by a first value according to an occurrence of a first event. The method also includes, in response to a determination that the modified multiplier value matches a first threshold, modifying, at the bit error injection circuit, the offset value according to an occurrence of a second event. The method further includes, in response to a determination that the modified offset value matches a second threshold, asserting, at the bit error injection circuit, an error injection signal. The method further includes asserting a first error pattern to be transmitted via a bus lane based on the error injection signal.

    Abstract translation: 一种方法包括根据第一事件的发生在位错误注入电路处修改乘数值乘以第一值。 该方法还包括响应于修改的乘数值与第一阈值匹配的确定，在位错误注入电路处修改根据第二事件的发生的偏移值。 该方法还包括响应于修改的偏移值与第二阈值匹配的确定，在位错误注入电路处断言错误注入信号。 该方法还包括基于误差注入信号来确定经由总线通道发送的第一错误模式。

    BAD WORDLINE/ARRAY DETECTION IN MEMORY
    86.
    发明申请
    BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
    BAD WORDLINE /阵列检测记忆

    公开(公告)号：US20130339823A1

    公开(公告)日：2013-12-19

    申请号：US13747842

    申请日：2013-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

    IPC: H03M13/05

    CPC classification number: H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

    Abstract: A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

    Abstract translation: 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

    HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
    87.
    发明申请
    HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
    在冗余存储系统中均衡恢复

    公开(公告)号：US20130191682A1

    公开(公告)日：2013-07-25

    申请号：US13792933

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Kevin C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

    IPC: G06F11/16

    CPC classification number: G06F11/1666 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

    Abstract: A computer implemented method for providing homogeneous recovery in a redundant memory system. The method includes receiving a notification that a memory channel has failed, where the memory channel is one of a plurality of memory channels in a memory system. New operations are blocked from starting on the memory channels in response to the notification, and any pending operations on the memory channels are completed in response to the notification. A recovery operation is performed on the memory channels in response to the completing. The new operations are started on at least a first subset of the memory channels in response to the recovery operation completing. The memory system is configured to operate with the first subset of the memory channels.

    Abstract translation: 一种用于在冗余存储器系统中提供均匀恢复的计算机实现的方法。 该方法包括接收存储器通道已经失败的通知，其中存储器通道是存储器系统中的多个存储器通道之一。 响应于通知，新的操作被阻止在内存通道上启动，响应于该通知，内存通道上的任何未完成的操作都被完成。 响应于完成，对存储器通道进行恢复操作。 响应于恢复操作完成，至少在存储器通道的第一子集上开始新的操作。 存储器系统被配置为与存储器通道的第一子集一起操作。

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