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    Combined rank and linear address incrementing utility for computer memory test operations
    1.
    发明授权
    Combined rank and linear address incrementing utility for computer memory test operations 有权
    用于计算机内存测试操作的组合级和线性地址递增实用程序

    公开(公告)号：US09437327B2

    公开(公告)日：2016-09-06

    申请号：US15063727

    申请日：2016-03-08

    Applicant: International Business Machines Corporation

    Inventor： Lawrence D. Curley ,  Patrick J. Meaney ,  George C. Wellwood

    IPC: G11C29/10 ,  G06F11/263 ,  G06F11/07

    CPC classification number: G11C29/10 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/2635 ,  G06F12/0607 ,  G11C5/04 ,  G11C29/18 ,  G11C29/20 ,  G11C2029/0409 ,  G11C2029/1806

    Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

    Abstract translation: 实施例包括组合的等级和线性存储器地址递增实用程序。 一个方面包括适用于作为中央处理单元（CPU）芯片的集成子系统的存储器控​​制器内实现的地址递增实用程序。 在这种片上实施例中，地址递增实用程序利用专用硬件，驻留芯片的固件和一个或多个存储器地址配置图来提高处理速度，效率和精度。 组合的等级和线性存储器地址递增实用程序被设计为有效地递增遍历所有单个位地址，以便逐级地划分为多个等级的大逻辑存储器空间。 地址增加实用程序顺序地产生所选择的等级的所有顺序存储器地址，然后移动到下一个级别并且顺序地产生该等级的所有存储器地址，并且等等，直到等级被处理。

    Dual asynchronous and synchronous memory system
    8.
    发明授权
    Dual asynchronous and synchronous memory system 有权
    双异步和同步存储系统

    公开(公告)号：US09318171B2

    公开(公告)日：2016-04-19

    申请号：US14501107

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

    IPC: G06F13/00 ,  G06F13/28 ,  G11C7/22 ,  G06F13/42 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4076

    CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

    Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

    Abstract translation: 用于存储器子系统中的双异步和同步存储器操作的计算机系统实现方法包括在存储器控制器和存储器缓冲器芯片之间建立同步通道。 模式选择器基于存储器缓冲器芯片的操作模式确定存储器缓冲器芯片的存储器域锁相环的参考时钟源。 基于同步的操作模式，将嵌套域锁相环的输出作为参考时钟源提供给存储器缓冲器芯片中的存储器域锁相环。 嵌套域锁相环可与存储器控制器的存储器控​​制器锁相环同步操作。 提供单独的参考时钟，独立于嵌套域锁相环作为基于异步操作模式的存储器域锁相环的参考时钟。

    Dual asynchronous and synchronous memory system
    9.
    发明授权
    Dual asynchronous and synchronous memory system 有权
    双异步和同步存储系统

    公开(公告)号：US09142272B2

    公开(公告)日：2015-09-22

    申请号：US13835521

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

    IPC: G06F9/26 ,  G11C7/22 ,  G06F13/42 ,  G11C5/04 ,  G11C11/4076

    CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

    Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

    Abstract translation: 实施例涉及双异步和同步存储器系统。 一个方面是一种系统，其包括存储器控制器和经由同步信道耦合到存储器控制器的存储器缓冲器芯片。 存储器缓冲器芯片包括被配置为与嵌套域中的存储器控​​制器同步通信的存储器缓冲器单元和被配置为与存储器域中的至少一个存储器接口端口通信的存储器缓冲适配器。 所述至少一个存储器接口端口可操作以访问至少一个存储器设备。 边界层连接到嵌套域和存储域，其中边界层可配置为在嵌套和存储器域之间以同步传输模式操作并且在嵌套和存储器域之间以异步传输模式操作。

    COMBINED RANK AND LINEAR ADDRESS INCREMENTING UTILITY FOR COMPUTER MEMORY TEST OPERATIONS
    10.
    发明申请
    COMBINED RANK AND LINEAR ADDRESS INCREMENTING UTILITY FOR COMPUTER MEMORY TEST OPERATIONS 有权
    组合的排名和线性地址增加计算机内存测试操作的实用性

    公开(公告)号：US20150262706A1

    公开(公告)日：2015-09-17

    申请号：US14211288

    申请日：2014-03-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Lawrence D. Curley ,  Patrick J. Meaney ,  George C. Wellwood

    IPC: G11C29/10 ,  G06F11/07 ,  G06F11/263

    CPC classification number: G11C29/10 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/2635 ,  G06F12/0607 ,  G11C5/04 ,  G11C29/18 ,  G11C29/20 ,  G11C2029/0409 ,  G11C2029/1806

    Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

    Abstract translation: 实施例包括组合的等级和线性存储器地址递增实用程序。 一个方面包括适用于作为中央处理单元（CPU）芯片的集成子系统的存储器控​​制器内实现的地址递增实用程序。 在这种片上实施例中，地址递增实用程序利用专用硬件，驻留芯片的固件和一个或多个存储器地址配置图来提高处理速度，效率和精度。 组合的等级和线性存储器地址递增实用程序被设计为有效地递增遍历所有单个位地址，以便逐级地划分为多个等级的大逻辑存储器空间。 地址增加实用程序顺序地产生所选择的等级的所有顺序存储器地址，然后移动到下一个级别并且顺序地产生该等级的所有存储器地址，并且等等，直到等级被处理。

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