公开(公告)号：US20200083357A1

公开(公告)日：2020-03-12

申请号：US16683979

申请日：2019-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/322 ,  H01L21/324 ,  H01L21/02 ,  H01L29/165 ,  H01L21/18

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US10566454B2

公开(公告)日：2020-02-18

申请号：US16032213

申请日：2018-07-11

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/165

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

公开(公告)号：US10453841B2

公开(公告)日：2019-10-22

申请号：US15285000

申请日：2016-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/04 ,  H01L29/78 ,  H01L21/18 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US10418463B2

公开(公告)日：2019-09-17

申请号：US15445344

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/18

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US10340368B2

公开(公告)日：2019-07-02

申请号：US16128945

申请日：2018-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/8234

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

公开(公告)号：US10319811B2

公开(公告)日：2019-06-11

申请号：US14949977

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Effendi Leobandung ,  Gen Tsutsui ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283 ,  H01L29/161 ,  H01L29/10

Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

公开(公告)号：US10243079B2

公开(公告)日：2019-03-26

申请号：US15639721

申请日：2017-06-30

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：US20190019883A1

公开(公告)日：2019-01-17

申请号：US16128945

申请日：2018-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/306 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

公开(公告)号：US10168075B2

公开(公告)日：2019-01-01

申请号：US15907812

申请日：2018-02-28

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/311 ,  F24S30/452 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  F24S20/61 ,  E04B1/343 ,  E04B1/346 ,  E04B7/16 ,  F24S30/00

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US10037944B2

公开(公告)日：2018-07-31

申请号：US15417940

申请日：2017-01-27

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/785 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.