公开(公告)号：US12249643B2

公开(公告)日：2025-03-11

申请号：US17482940

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew Gaul ,  Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Christopher J. Waskiewicz

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

公开(公告)号：US20240282860A1

公开(公告)日：2024-08-22

申请号：US18171528

申请日：2023-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Susan Ng Emans ,  Andrew M. Greene

IPC: H01L29/78 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/3086 ,  H01L29/66795 ,  H01L21/3065

Abstract: A finFET that includes a nonlinear channel is presented. The nonlinear channel includes one or more arced, curved, segmented, or the like, sidewall(s) that define a channel width and a channel length. The nonlinear channel provides a relatively increased channel length compared to a linear fin that is orientated orthogonal to the gate width. As such, channel length of the nonlinear channel may be relatively increased within the confines of the gate. In other words, short channel effects may be limited due to a reduced electric field along the nonlinear channel due to the relatively increased channel or fin length within the footprint of the gate.

公开(公告)号：US20240213315A1

公开(公告)日：2024-06-27

申请号：US18087990

申请日：2022-12-23

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Curtis S. Durfee ,  Oleg Gluschenkov ,  Andrew Gaul

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/42392

Abstract: A semiconductor structure includes a gate region, a source/drain region, and a nanosheet semiconductor layer extending continuously across the gate region and the source/drain region. The nanosheet semiconductor layer includes a first portion in the gate region and a second portion in the source/drain region. The source/drain region includes a cladded epitaxial layer wrapping around the second portion of the nanosheet semiconductor layer.

公开(公告)号：US11908743B2

公开(公告)日：2024-02-20

申请号：US17485601

申请日：2021-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Andrew M. Greene ,  Julien Frougier ,  Ruqiang Bao ,  Jingyun Zhang ,  Miaomiao Wang ,  Dechao Guo

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

公开(公告)号：US11710768B2

公开(公告)日：2023-07-25

申请号：US17303275

申请日：2021-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric Miller ,  Indira Seshadri ,  Andrew M. Greene ,  Julien Frougier ,  Veeraraghavan S. Basker

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An apparatus including a substrate and a first nanosheet device located on the substrate. A second nanosheet device is located on the substrate, where the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device and the at least one first gate has a first width. At least one second gate located on the second nanosheet device and the at least one second gate has a second width. The first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device. The diffusion break prevents the first nanosheet device from contacting the second nanosheet device, and the diffusion break has a third width. The third width is larger than the first width and the second width.

公开(公告)号：US20230197530A1

公开(公告)日：2023-06-22

申请号：US17554765

申请日：2021-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Andrew M. Greene ,  Veeraraghavan S. Basker ,  Jingyun Zhang ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1207 ,  H01L27/1211

Abstract: A semiconductor device is provided. The semiconductor device includes a top field effect device over a bottom field effect device, and a bottom contact electrically connecting a bottom source/drain of the bottom field effect device to a first buried power rail. The semiconductor device further includes a bottom contact cap on the bottom contact, and a trench liner on opposite sides of the bottom contact cap and the bottom contact.

公开(公告)号：US20230178621A1

公开(公告)日：2023-06-08

申请号：US17544328

申请日：2021-12-07

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Yao Yao ,  Andrew M. Greene ,  Veeraraghavan S. Basker ,  Pietro Montanini ,  Jingyun Zhang ,  Robert Robison

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418

Abstract: A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

公开(公告)号：US20230171114A1

公开(公告)日：2023-06-01

申请号：US17537605

申请日：2021-11-30

Applicant: International Business Machines Corporation

Inventor： Dallas Lea ,  Yann Mignot ,  Marc A. Bergendahl ,  Alex Joseph Varghese ,  Sean Teehan ,  Andrew M. Greene ,  Matthew T. Shoudy

IPC: H04L9/32 ,  H03K3/03 ,  H03H7/06 ,  H03H7/01 ,  H03K3/037

CPC classification number: H04L9/3278 ,  H03K3/0315 ,  H03H7/06 ,  H03H7/0161 ,  H03K3/037

Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.

公开(公告)号：US20230139399A1

公开(公告)日：2023-05-04

申请号：US17516505

申请日：2021-11-01

Applicant: International Business Machines Corporation

Inventor： HUIMEI ZHOU ,  Andrew M. Greene ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Robert Robison ,  JUNTAO LI ,  Richard A. Conti ,  FEE LI LIE

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

公开(公告)号：US20230060619A1

公开(公告)日：2023-03-02

申请号：US17411597

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Veeraraghavan S. Basker

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.