公开(公告)号：US20190206864A1

公开(公告)日：2019-07-04

申请号：US16272844

申请日：2019-02-11

申请人： International Business Machines Corporation

发明人： Hong He ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC分类号： H01L27/088 ,  H01L21/265 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

摘要： A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US10170327B2

公开(公告)日：2019-01-01

申请号：US15613774

申请日：2017-06-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L21/00 ,  H01L21/308 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3213

摘要： Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.

公开(公告)号：US20180223522A1

公开(公告)日：2018-08-09

申请号：US15907812

申请日：2018-02-28

申请人： International Business Machines Corporation

发明人： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC分类号： E04B1/344 ,  E04B1/346 ,  E04B7/16 ,  E04B1/343

CPC分类号： F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

摘要： A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US09953916B2

公开(公告)日：2018-04-24

申请号：US15423923

申请日：2017-02-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC分类号： F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

摘要： A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US20170194463A1

公开(公告)日：2017-07-06

申请号：US15464495

申请日：2017-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC分类号： H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L21/225 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

摘要： A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

公开(公告)号：US20170194138A1

公开(公告)日：2017-07-06

申请号：US14984845

申请日：2015-12-30

申请人： International Business Machines Corporation ,  Matheson Tri-Gas, Inc.

发明人： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki ,  Yunpeng Yin ,  Zhengmao Zhu

IPC分类号： H01L21/02 ,  H01L21/225 ,  H01L21/306

CPC分类号： H01L21/0262 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

摘要： A selective semiconductor deposition process that employs an alternating sequence of a deposition step and an etch step. During each deposition step, a semiconductor material is deposited on single crystalline surfaces at a greater deposition rate than on insulator surfaces. A combination of hydrogen chloride and a germanium-containing gas is employed within each etch step. The germanium-containing gas is employed to enhance the etch rate of hydrogen chloride, thereby enabling an effective etch process at temperatures as low as 380° C. Deposited semiconductor material is removed from above insulator surfaces, while a fraction of the deposited semiconductor material remains on semiconductor surfaces after each etch step, thereby providing a selective deposition of the semiconductor material.

公开(公告)号：US09627263B1

公开(公告)日：2017-04-18

申请号：US14953461

申请日：2015-11-30

申请人： International Business Machines Corporation

发明人： Hong He ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC分类号： H01L27/12 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/26533 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/785

摘要： A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US20170033103A1

公开(公告)日：2017-02-02

申请号：US15292187

申请日：2016-10-13

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/165

CPC分类号： H01L27/0886 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76202 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656

摘要： A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

摘要翻译： 一种具有异质硅堆叠的半导体器件，其中所述异质硅堆叠至少包括基极层，掺杂硅层和未掺杂的硅层。 半导体器件还包括在掺杂的氧化硅鳍层和未掺杂的氧化硅鳍层上面的多个硅散热片，其中多个硅散热片沿着多个硅散热片的高度具有均匀的宽度，并且其中多个 硅散热片具有多个硬掩模盖。

公开(公告)号：US20160351447A1

公开(公告)日：2016-12-01

申请号：US14727132

申请日：2015-06-01

申请人： International Business Machines Corporation

发明人： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

摘要： A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

摘要翻译： 制造自对准通孔结构的方法包括在下金属布线层上的ILD层上形成三层掩模，所述三层掩模包括第一绝缘层和第二绝缘层以及绝缘层之间的金属层; 通过所述第一绝缘层和金属层限定沟槽图案，所述沟槽图案具有第一宽度; 在所述沟槽图案上的光刻掩模中限定第一通孔图案，所述第一通孔图案具有大于所述第一宽度的第二宽度; 在沟槽图案的暴露的侧壁上生长金属覆盖层，以将第一宽度减小到限定第二通孔图案的第三宽度; 将沟槽图案转移到ILD层中以形成沟槽; 并且将第二通孔图案通过ILD层转移到金属布线层中以形成通孔。

公开(公告)号：US09330962B2

公开(公告)日：2016-05-03

申请号：US14457176

申请日：2014-08-12

申请人： International Business Machines Corporation

发明人： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L45/00 ,  H01L21/02 ,  H01L23/498

CPC分类号： H01L21/768 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/498 ,  H01L29/0692 ,  H01L45/1691 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.