公开(公告)号：US11594624B2

公开(公告)日：2023-02-28

申请号：US16218892

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Chia-Ching Lin ,  Tanay Gosavi ,  Uygar Avci ,  Ian Young

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423

Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.

公开(公告)号：US11575083B2

公开(公告)日：2023-02-07

申请号：US15943461

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Ian Young ,  Dmitri Nikonov ,  Chia-Ching Lin

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  H01L43/14 ,  B82Y25/00

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.

公开(公告)号：US11430942B2

公开(公告)日：2022-08-30

申请号：US16021425

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F41/30 ,  H01F10/32 ,  G11C11/16

Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.

公开(公告)号：US11374163B2

公开(公告)日：2022-06-28

申请号：US16012668

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10

Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.

公开(公告)号：US20220199758A1

公开(公告)日：2022-06-23

申请号：US17132970

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Jason C. Retasket ,  Matthew V. Metz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Kaan Oguz ,  Uygar E. Avci ,  Edward Johnson

IPC: H01L49/02 ,  H01L29/51 ,  H01L23/522 ,  H01L27/06 ,  H01L29/78

Abstract: Capacitors with a carbon-based electrode layer in contact with a ferroelectric insulator. The insulator may be a perovskite oxide. Low reactivity of the carbon-based electrode may improve stability of a ferroelectric capacitor. A carbon-based electrode layer may be predominantly carbon and have a low electrical resistivity. A carbon-based electrode layer may be the only layer of an electrode, or it may be a barrier between the insulator and another electrode layer. Both electrodes of a capacitor may include a carbon-based electrode layer, or a carbon-based electrode layer may be included in only one electrode.

公开(公告)号：US20210398993A1

公开(公告)日：2021-12-23

申请号：US16906217

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC: H01L27/11507 ,  H01L23/522 ,  H01L21/768

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US20200286984A1

公开(公告)日：2020-09-10

申请号：US16296035

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/11507

Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

公开(公告)号：US20200286685A1

公开(公告)日：2020-09-10

申请号：US16294811

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

公开(公告)号：US20190386202A1

公开(公告)日：2019-12-19

申请号：US16012668

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.

公开(公告)号：US20190305212A1

公开(公告)日：2019-10-03

申请号：US15943461

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Ian Young ,  Dmitri Nikonov ,  Chia-Ching Lin

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.