公开(公告)号：US20100006942A1

公开(公告)日：2010-01-14

申请号：US12458391

申请日：2009-07-10

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L23/522 ,  H01L27/12

CPC分类号： H01L23/522 ,  H01L27/11 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

摘要翻译： 提供一种互连结构和采用该互连结构的电子设备。 用于集成结构的互连结构包括设置在基板上的第一和第二接触插塞以及插入在第一和第二接触插塞的侧壁之间并且被配置为电连接第一和第二接触插塞的连接图案。

公开(公告)号：US07170133B2

公开(公告)日：2007-01-30

申请号：US10977036

申请日：2004-10-28

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

摘要： A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel region is interposed between the pair of the source/drain regions. The active region has a mesa disposed across the channel region. The mesa extends to the source/drain regions. A gate electrode is disposed to cross the active region along the direction across the mesa.

摘要翻译： 晶体管及其制造方法：晶体管包括设置在半导体衬底中以限定有源区的隔离层。 一对源极/漏极区域设置在有源区域中，彼此间隔开。 沟道区域插入在一对源极/漏极区域之间。 有源区域具有穿过沟道区域设置的台面。 台面延伸到源极/漏极区域。 栅电极设置成跨过台面的方向跨越有源区。

公开(公告)号：US20050110074A1

公开(公告)日：2005-05-26

申请号：US10977036

申请日：2004-10-28

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

摘要： A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel region is interposed between the pair of the source/drain regions. The active region has a mesa disposed across the channel region. The mesa extends to the source/drain regions. A gate electrode is disposed to cross the active region along the direction across the mesa.

摘要翻译： 晶体管及其制造方法：晶体管包括设置在半导体衬底中以限定有源区的隔离层。 一对源极/漏极区域设置在有源区域中，彼此间隔开。 沟道区域插入在一对源极/漏极区域之间。 有源区域具有穿过沟道区域设置的台面。 台面延伸到源极/漏极区域。 栅电极设置成跨过台面的方向跨越有源区。

公开(公告)号：US07825472B2

公开(公告)日：2010-11-02

申请号：US12219278

申请日：2008-07-18

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L27/12

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

摘要翻译： 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US07592625B2

公开(公告)日：2009-09-22

申请号：US11502397

申请日：2006-08-11

申请人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

发明人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L31/112

CPC分类号： G11C11/412 ,  G11C11/413 ,  Y10S257/903

摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 该器件可以包括包括外围区域和单元阵列区域的半导体衬底，其中，单元阵列区域中的衬底可以比周边区域低的凹槽，堆叠在单元阵列区域中的多个单元晶体管层，以及多个单元阵列区域 形成在外围区域的外围电路晶体管。 单元晶体管层可以形成在比周边区域更低的电池阵列区域中。

公开(公告)号：US07563683B2

公开(公告)日：2009-07-21

申请号：US11611719

申请日：2006-12-15

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

摘要： Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N− ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N+ ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.

摘要翻译： 公开了一种用于制造场效应晶体管的栅极的方法。 该方法包括：a）在硅衬底上形成场氧化物层，然后施加光致抗蚀剂层以限定栅极，b）使用光致抗蚀剂层作为掩模蚀刻硅衬底，c）依次沉积栅极氧化物层和 在硅衬底的整个表面上的栅极多晶硅层，并使用光致抗蚀剂层限定栅极; d）使用光致抗蚀剂层作为掩模蚀刻所得到的硅衬底，以形成栅极并通过离子形成N-离子区域 注入，以及e）沉积和蚀刻回氧化物层以形成侧壁氧化物层，并通过离子注入形成N +离子区域。 因此，通过蚀刻硅衬底来制造栅极。 因此，栅极的长度减小，使得不仅可以使单元区域更小，而且可以防止短沟道效应。

公开(公告)号：US07312144B2

公开(公告)日：2007-12-25

申请号：US10932416

申请日：2004-09-02

申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC分类号： H01L21/4763

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

摘要： An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

公开(公告)号：US20070087491A1

公开(公告)日：2007-04-19

申请号：US11611719

申请日：2006-12-15

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

摘要： Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N− ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N+ ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.

摘要翻译： 公开了一种用于制造场效应晶体管的栅极的方法。 该方法包括：a）在硅衬底上形成场氧化物层，然后施加光致抗蚀剂层以限定栅极，b）使用光致抗蚀剂层作为掩模蚀刻硅衬底，c）依次沉积栅极氧化物层和 在硅衬底的整个表面上的栅极多晶硅层，并使用光致抗蚀剂层限定栅极; d）使用光致抗蚀剂层作为掩模蚀刻所得的硅衬底，以形成栅极并形成N + >离子区域，以及e）通过离子注入沉积和蚀刻回氧化物层以形成侧壁氧化物层并形成N + +离子区域。 因此，通过蚀刻硅衬底来制造栅极。 因此，栅极的长度减小，使得不仅可以使单元区域更小，而且可以防止短沟道效应。

公开(公告)号：US20070069282A1

公开(公告)日：2007-03-29

申请号：US11559758

申请日：2006-11-14

申请人： Hyung Kwon ,  Soon-Moon Jung

发明人： Hyung Kwon ,  Soon-Moon Jung

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  Y10S438/981

摘要： Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一栅极图案。 第一栅极图案的顶部宽度基本上等于或小于第一栅极图案的底部宽度。 第二栅极图案设置在半导体衬底的第二有源区上。 第二栅极图案具有比第二栅极图案的底部宽度宽的顶部宽度。 通过在形成在半导体衬底的第一有源区上的第一栅极绝缘层上形成第一栅极图案来制造半导体器件。 在包括第一栅极图案的半导体基板上形成掩模绝缘层。 通过图案化掩模绝缘层来形成分别暴露半导体衬底的第二和第三有源区的第一和第二栅极开口。 第二和第三栅极绝缘层分别形成在暴露在第一和第二栅极开口中的第二和第三有源区上。 分别在第一和第二栅极开口中形成第二和第三栅极图案，并且去除掩模绝缘层。

公开(公告)号：US20070047371A1

公开(公告)日：2007-03-01

申请号：US11502397

申请日：2006-08-11

申请人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

发明人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C11/413 ,  Y10S257/903

摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 该器件可以包括包括外围区域和单元阵列区域的半导体衬底，其中，单元阵列区域中的衬底可以比周边区域低的凹槽，堆叠在单元阵列区域中的多个单元晶体管层，以及多个单元阵列区域 形成在外围区域的外围电路晶体管。 单元晶体管层可以形成在比周边区域更低的电池阵列区域中。