公开(公告)号：US20070069282A1

公开(公告)日：2007-03-29

申请号：US11559758

申请日：2006-11-14

申请人： Hyung Kwon ,  Soon-Moon Jung

发明人： Hyung Kwon ,  Soon-Moon Jung

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  Y10S438/981

摘要： Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一栅极图案。 第一栅极图案的顶部宽度基本上等于或小于第一栅极图案的底部宽度。 第二栅极图案设置在半导体衬底的第二有源区上。 第二栅极图案具有比第二栅极图案的底部宽度宽的顶部宽度。 通过在形成在半导体衬底的第一有源区上的第一栅极绝缘层上形成第一栅极图案来制造半导体器件。 在包括第一栅极图案的半导体基板上形成掩模绝缘层。 通过图案化掩模绝缘层来形成分别暴露半导体衬底的第二和第三有源区的第一和第二栅极开口。 第二和第三栅极绝缘层分别形成在暴露在第一和第二栅极开口中的第二和第三有源区上。 分别在第一和第二栅极开口中形成第二和第三栅极图案，并且去除掩模绝缘层。

公开(公告)号：US08227919B2

公开(公告)日：2012-07-24

申请号：US12458391

申请日：2009-07-10

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L27/12

CPC分类号： H01L23/522 ,  H01L27/11 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

摘要翻译： 提供一种互连结构和采用该互连结构的电子设备。 用于集成结构的互连结构包括设置在基板上的第一和第二接触插塞以及插入在第一和第二接触插塞的侧壁之间并且被配置为电连接第一和第二接触插塞的连接图案。

公开(公告)号：US20120009767A1

公开(公告)日：2012-01-12

申请号：US13236000

申请日：2011-09-19

申请人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

发明人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC分类号： H01L21/20

CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US08048727B2

公开(公告)日：2011-11-01

申请号：US12687545

申请日：2010-01-14

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L21/00

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US07982221B2

公开(公告)日：2011-07-19

申请号：US12537521

申请日：2009-08-07

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L29/76

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20110163411A1

公开(公告)日：2011-07-07

申请号：US13049495

申请日：2011-03-16

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L27/08

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US07936002B2

公开(公告)日：2011-05-03

申请号：US12456391

申请日：2009-06-16

申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

公开(公告)号：US20100240209A1

公开(公告)日：2010-09-23

申请号：US12792912

申请日：2010-06-03

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/28

CPC分类号： H01L21/26506 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/167 ,  H01L29/34 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7883 ,  H01L29/792

摘要： Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.

摘要翻译： 提供半导体器件及其形成方法。 半导体器件包括还包括氢注入层和在氢注入层上形成的包括第一绝缘层，电荷存储层，第二绝缘层和导电层的栅极结构的衬底。

公开(公告)号：US07795651B2

公开(公告)日：2010-09-14

申请号：US12024459

申请日：2008-02-01

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L31/112

CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

公开(公告)号：US20100006942A1

公开(公告)日：2010-01-14

申请号：US12458391

申请日：2009-07-10

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L23/522 ,  H01L27/12

CPC分类号： H01L23/522 ,  H01L27/11 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

摘要翻译： 提供一种互连结构和采用该互连结构的电子设备。 用于集成结构的互连结构包括设置在基板上的第一和第二接触插塞以及插入在第一和第二接触插塞的侧壁之间并且被配置为电连接第一和第二接触插塞的连接图案。