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81.发明授权公开(公告)号：US08023325B2
公开(公告)日：2011-09-20
申请号：US13019048
申请日：2011-02-01
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
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公开(公告)号：US20080091900A1
公开(公告)日：2008-04-17
申请号：US11948865
申请日：2007-11-30
申请人： Tsutomu IMAI , Akira Kanehira , Kunihiro Katayama
发明人： Tsutomu IMAI , Akira Kanehira , Kunihiro Katayama
IPC分类号： G06F12/00
CPC分类号： G06F21/10 , G06F12/1416 , G06F21/725 , G06F2221/2137 , G06F2221/2153
摘要： The disclosed invention effectively prevents fraudulent access to data whose usage is restricted to a time limit, such access attempted by manipulating the clock internal to a playback device and a terminal device. A nonvolatile memory device of the invention comprises a control circuit and a nonvolatile memory circuit which includes a storage region for restriction information to restrict access to contents information provided by web-based rental service. The restriction information includes access time limit information and access time stamp information. The control circuit performs an access decision action which comprises deciding whether access to the contents information is enabled or disabled, based on real time information which is supplied externally and the restriction information, and updating the access time stamp information to the realtime information. The control circuit decides that access is disabled if the real time information is later than the access time limit given by the access time limit information or if the real time information is earlier than the access time stamp given by the access time stamp information; otherwise, the control circuit decides that the access is enabled. The control circuit performs the access decision action, at least, at the start of access to said contents information and at the end of the access.
摘要翻译： 所公开的发明有效地防止对使用限制在时间限制的数据的欺骗性访问，这种访问通过操纵播放设备和终端设备内部的时钟而尝试。 本发明的非易失性存储装置包括控制电路和非易失性存储器电路，其包括用于限制对由基于web的租赁服务提供的内容信息的访问的限制信息的存储区域。 限制信息包括访问时间限制信息和访问时间戳信息。 控制电路执行接入决策动作，其包括基于外部提供的实时信息和限制信息来决定对内容信息的访问是否被启用或禁用，以及将访问时间戳信息更新为实时信息。 如果实时信息晚于由访问时间限制信息给出的访问时间限制或者实时信息早于由访问时间戳信息给出的访问时间戳，则控制电路决定访问被禁用; 否则，控制电路确定访问被启用。 至少在开始访问所述内容信息和访问结束时，控制电路执行访问决策动作。
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公开(公告)号：US07234087B2
公开(公告)日：2007-06-19
申请号：US10748156
申请日：2003-12-31
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.
摘要翻译： 获得高速存储器访问和使用单个纠错装置的透明错误检测和校正。 主计算机将扇区数据写入第一存储器和第二存储器之一，以及第一和第二存储器中的另一个中的下一扇区数据。 扇区数据从第一存储器和第二存储器之一读出到主计算机，并且同时从第一存储器和第二存储器中的另一个读出下一个扇区数据，并且在纠错装置中执行错误检测和校正 。 在下一周期中，将从第一存储器和第二存储器之一读出的扇区数据输出到主计算机，同时，从第一计算机和第二计算机之一读出的下一个扇区数据的错误检测和纠错 在纠错装置中执行。
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公开(公告)号：US20070101047A1
公开(公告)日：2007-05-03
申请号：US10561795
申请日：2004-12-22
申请人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
发明人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
CPC分类号： G11C16/349 , G06F12/0246 , G11C16/3427
摘要： A memory apparatus having a rewritable nonvolatile memory, and a control circuit. The memory apparatus brings logical addresses into correspondence with physical addresses of the nonvolatile memory and retains a piece of number-of-rewrites information for each logical address. The control circuit can perform a replacement process of a piece of memory information on the nonvolatile memory. In the replacement process, a given logical address judged to have a small number of rewrites based on the number-of-rewrites information is replaced so as to correspond to a different physical address and then data is transferred according to the replacement. Even when data of the logical address smaller in the number of rewrites is assigned to the different physical address, the number of rewrites of the region is still grasped as the number of rewrites of the logical address. The data of the logical address is maintained in a condition such that it can be easily targeted for the rewrite by the replacement process even in the place to which the data is transferred. Thus, a memory cell is made less prone to accumulatively suffering disturb owing to rewrite.
摘要翻译： 具有可重写非易失性存储器的存储装置和控制电路。 存储装置使逻辑地址与非易失性存储器的物理地址相对应，并且为每个逻辑地址保留一段重写数量的信息。 控制电路可以在非易失性存储器上执行一条存储器信息的替换处理。 在替换处理中，基于重写信息信息判断为具有少量重写的给定逻辑地址被替换为对应于不同的物理地址，然后根据替换来传送数据。 即使将重写次数较小的逻辑地址的数据分配给不同的物理地址，也可以将该区域的重写次数作为逻辑地址的重写次数来掌握。 逻辑地址的数据被保持在这样的状态，使得即使在数据被传送到的地方也可以容易地通过替换处理进行重写。 因此，由于重写，存储器单元不容易累积地受到干扰。
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85.发明申请公开(公告)号：US20060062045A1
公开(公告)日：2006-03-23
申请号：US11206995
申请日：2005-08-19
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
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86.发明授权公开(公告)号：US06952752B2
公开(公告)日：2005-10-04
申请号：US10683066
申请日：2003-10-14
CPC分类号： G06F3/0613 , G06F3/0601 , G06F3/064 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/023 , G06F12/0246 , G06F2003/0694 , G06F2212/7208
摘要： A flash memory based file memory device built in an information processing apparatus enables fast file access. The file memory device is provided with a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device and a data access width smaller than the data bus, a file division unit for dividing file data that consists of one or more unit storage data blocks into combined blocks that consists of a combination of arbitrary unit storage data blocks, a data distribution unit for combining arbitrarily data on the data bus in terms of the unit data size equal to the data access width and making the combined data correspondent to an arbitrary combination of memory element groups equal in number to the unit size data, and a control unit for controlling the data distribution unit such that each combined block is stored in the file memory device by being correspondent to one of the arbitrary combinations of memory element groups.
摘要翻译： 内置于信息处理装置中的基于闪速存储器的文件存储装置能够实现文件快速访问。 所述文件存储装置设置有具有大于所述存储装置的数据总线宽度的单位擦除块大小和小于所述数据总线的数据访问宽度的存储元件组的并行布置，用于分割文件数据的文件数据的文件分割单元 由一个或多个单元存储数据块组成由组合的任意单位存储数据块组成的组合块，数据分配单元，用于根据与数据存取宽度相等的单位数据大小在数据总线上任意组合数据，以及 使得组合数据对应于与单位大小数据数量相等的存储单元组的任意组合;以及控制单元，用于控制数据分配单元，使得每个组合块通过对应于 存储元件组的任意组合。
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公开(公告)号：US06917547B2
公开(公告)日：2005-07-12
申请号：US10616955
申请日：2003-07-11
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
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公开(公告)号：US06701471B2
公开(公告)日：2004-03-02
申请号：US09750707
申请日：2001-01-02
IPC分类号： G11C2900
CPC分类号： G06F11/1008
摘要： High-speed memory access and transparent error detection and correction using a single error correcting means are obtained and processed by an external storage device of a host computer when sector data having an arbitrary byte width are accessed continuously according to a size of a sector unit. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed, thereby greatly reducing the time required for error detection and error correction, and high speed memory access can be obtained.
摘要翻译： 当根据扇区单元的大小连续访问具有任意字节宽度的扇区数据时，由主计算机的外部存储设备获得并处理高速存储器访问和使用单个纠错装置的透明错误检测和校正。 因此，主计算机总是读取扇区数据，同时执行错误检测和下一个扇区数据的纠错，从而大大减少了错误检测和纠错所需的时间，高速存储器存取可以 得到。
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89.发明授权公开(公告)号：US06683812B2
公开(公告)日：2004-01-27
申请号：US10304046
申请日：2002-11-26
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.
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公开(公告)号：US06388920B2
公开(公告)日：2002-05-14
申请号：US09886133
申请日：2001-06-22
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
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