公开(公告)号：US06459621B1

公开(公告)日：2002-10-01

申请号：US09931030

申请日：2001-08-17

申请人： Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

发明人： Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

IPC分类号： G11C1134

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

摘要翻译： 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制，直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式（粗写），其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高，并且第二写入 模式（高精度写入），其中阈值电压的变化量相对低。 与高精度模式相比，改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此，使用粗写入模式时的验证操作数量很少，因此可以加快整个写入操作。

公开(公告)号：US06438028B1

公开(公告)日：2002-08-20

申请号：US09616072

申请日：2000-07-13

申请人： Takashi Kobayashi ,  Hideaki Kurata ,  Naoki Kobayashi ,  Hitoshi Kume ,  Katsutaka Kimura ,  Shunichi Saeki

发明人： Takashi Kobayashi ,  Hideaki Kurata ,  Naoki Kobayashi ,  Hitoshi Kume ,  Katsutaka Kimura ,  Shunichi Saeki

IPC分类号： G11C700

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

摘要翻译： 在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。 在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极， 栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极 并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

公开(公告)号：US06396736B1

公开(公告)日：2002-05-28

申请号：US09715106

申请日：2000-11-20

申请人： Yusuke Jyouno ,  Takayuki Kawahara ,  Katsutaka Kimura

发明人： Yusuke Jyouno ,  Takayuki Kawahara ,  Katsutaka Kimura

IPC分类号： G11C1604

CPC分类号： G11C11/005 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

摘要翻译： 为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个 与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。 以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。 在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换 到两位信息。

公开(公告)号：US06330178B1

公开(公告)日：2001-12-11

申请号：US09558104

申请日：2000-04-25

申请人： Takeshi Sakata ,  Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Katsutaka Kimura ,  Masanori Isoda ,  Kazuhiko Kajigaya

发明人： Takeshi Sakata ,  Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Katsutaka Kimura ,  Masanori Isoda ,  Kazuhiko Kajigaya

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

摘要翻译： 由于铁电存储器件不能采用在DRAM中广泛使用的VCC / 2预充电方案，其阵列噪声和功耗很大。 此外，由于其疲劳和压印，铁电电容器的特性劣化。 为了避免这种情况，数据线对被预充电到两个电压VCC和VSS。 结果，存储单元阵列MCA中的数据线上的电压以VCC / 2为中心对称地变化，从而减少阵列噪声。 此外，当基于不同预充电电压的数据线之间的电荷共享来执行早期感测和早期预充电操作时，可以降低功耗。 此外，当为各个数据线切换预充电电压时，在存储单元中的铁电电容器中交替执行反向和非反向极化以抑制其疲劳和压印。

公开(公告)号：US06278628B1

公开(公告)日：2001-08-21

申请号：US09532734

申请日：2000-03-22

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

IPC分类号： G11C506

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882

摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

摘要翻译： 在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。 当数据线被放大时，数据线字线不平衡产生大的噪声，这很可能引起数据线上的非常小的信号的恶化和数据的错误放大。 连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。 当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。 因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

公开(公告)号：US06201735B1

公开(公告)日：2001-03-13

申请号：US09362719

申请日：1999-07-29

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 此外，因为负电压被施加到字线，所以可以降低编程数据时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

公开(公告)号：US06181603B2

公开(公告)日：2001-01-30

申请号：US09339960

申请日：1999-06-25

申请人： Yusuke Jyouno ,  Takayuki Kawahara ,  Katsutaka Kimura

发明人： Yusuke Jyouno ,  Takayuki Kawahara ,  Katsutaka Kimura

IPC分类号： G11C1606

CPC分类号： G11C11/005 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

摘要翻译： 为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个 与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。 以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。 在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换 到两位信息。

公开(公告)号：US6101123A

公开(公告)日：2000-08-08

申请号：US288313

申请日：1999-04-08

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C8/08 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory essentially consisting of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 特别是由于用于字线的负电压，可以降低编程数据时的漏极电压，从而可以减轻沟道部分的栅极氧化膜的劣化。

公开(公告)号：US6097623A

公开(公告)日：2000-08-01

申请号：US125545

申请日：1998-08-28

申请人： Takeshi Sakata ,  Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Katsutaka Kimura ,  Masanori Isoda ,  Kazuhiko Kajigaya

发明人： Takeshi Sakata ,  Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Katsutaka Kimura ,  Masanori Isoda ,  Kazuhiko Kajigaya

IPC分类号： G11C11/22 ,  G11C7/00

CPC分类号： G11C11/22

摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge share between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

摘要翻译： PCT No.PCT / JP96 / 00464 Sec。 371日期1998年8月28日 102（e）1998年8月28日PCT PCT 1996年2月28日PCT公布。 公开号WO97 / 32311 日期1997年9月4日由于铁电存储器件不能采用DRAM广泛使用的VCC / 2预充电方案，其阵列噪声和功耗很大。 此外，由于其疲劳和压印，铁电电容器的特性劣化。 为了避免这种情况，数据线对被预充电到两个电压VCC和VSS。 结果，存储单元阵列MCA中的数据线上的电压以VCC / 2为中心对称地变化，从而减少阵列噪声。 此外，当基于不同预充电电压的数据线之间的电荷共享来执行早期感测和早期预充电操作时，可以降低功耗。 此外，当为各个数据线切换预充电电压时，在存储单元中的铁电电容器中交替执行反向和非反向极化以抑制其疲劳和压印。

公开(公告)号：US5910911A

公开(公告)日：1999-06-08

申请号：US774907

申请日：1996-12-27

申请人： Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Takeshi Sakata ,  Takayuki Kawahara ,  Katsutaka Kimura

发明人： Tomonori Sekiguchi ,  Hiroki Fujisawa ,  Takeshi Sakata ,  Takayuki Kawahara ,  Katsutaka Kimura

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C7/1045 ,  G11C11/22

摘要： Disclosed is a semiconductor memory having memory cells, each containing a selection transistor and a capacitor using a ferroelectric film, which memory can be operated in both volatile and nonvolatile modes (e.g., a shadow RAM). A common plate electrode is used for the capacitors of the plurality of memory cells, and this common plate electrode is held at a fixed (constant) voltage. The memory has two data lines for each memory cell, and a sense amplifier connected between the two data lines. Volatile or nonvolatile operation is established depending on the voltage applied to the amplifier. The voltage applied to the amplifier is increased and the ferroelectric capacitor is completely polarized to write nonvolatile information; to write volatile information, this voltage is decreased and polarization reversal is minimized. The memory can have a mode switching circuit which changes the power supply voltage to the amplifier, to change mode of operation between volatile and nonvolatile modes, and an internal voltage generator to generate voltages, inter alia, for read and write in both the volatile and nonvolatile modes of operation. The memory performs store and recall operations at a high speed and decreased power consumption; and fatigue of the ferroelectric capacitor when performing volatile write decreases, and the number of rewritings can be increased.

摘要翻译： 公开了一种具有存储单元的半导体存储器，每个存储单元包含选择晶体管和使用铁电体膜的电容器，该存储器可以在易失性和非易失性模式（例如，影子RAM）中操作。 公共板电极用于多个存储单元的电容器，并且该公共板电极保持在固定（恒定）电压。 存储器具有用于每个存储单元的两条数据线，以及连接在两条数据线之间的读出放大器。 根据施加到放大器的电压建立易失性或非易失性操作。 施加到放大器的电压增加，并且铁电电容器被完全极化以写入非易失性信息; 写入易失性信息，该电压降低，极化反转最小化。 存储器可以具有模式切换电路，其改变放大器的电源电压，以改变易失性和非易失性模式之间的操作模式，以及内部电压发生器，以产生电压，特别是用于在易失性和易失性模式下进行读取和写入 非易失性操作模式。 存储器以高速度进行存储和调用操作并降低功耗; 并且当执行易失性写入时铁电电容器的疲劳减小，并且可以增加重写次数。