公开(公告)号：US20140183619A1

公开(公告)日：2014-07-03

申请号：US14165611

申请日：2014-01-28

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7827

Abstract: A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided. A charging trapping layer is formed conformally on the protruding strips. A conductive layer is formed conformally on the charging trapping layer. A thin hard mask is conformally deposited on the conductive layer, wherein a plurality of trenches are formed between the thin hard mask on the protruding strips. A patterned photo resist is formed on the thin hard mask, wherein the patterned photo resist fills into the trenches. The thin hard mask is patterned according to the patterned photo resist to form a patterned hard mask layer and expose a portion of the conductive layer. The conductive layer is patterned for removing the exposed portion of the conductive layer to form a patterned conductive layer and expose a portion of the charging trapping layer.

Abstract translation: 公开了半导体器件的制造方法。 提供了具有垂直形成的多个突出条的基板。 充电捕获层在突出条上保形地形成。 在充电捕集层上保形地形成导电层。 在导电层上共形沉积薄的硬掩模，其中在突出条上的薄硬掩模之间形成多个沟槽。 在薄的硬掩模上形成图案化的光致抗蚀剂，其中图案化的光致抗蚀剂填充到沟槽中。 根据图案化的光致抗蚀剂对薄的硬掩模进行图案化，以形成图案化的硬掩模层并暴露导电层的一部分。 图案化导电层以去除导电层的暴露部分以形成图案化的导电层并暴露一部分充电捕获层。

公开(公告)号：US20140175532A1

公开(公告)日：2014-06-26

申请号：US13727139

申请日：2012-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD

Inventor： Shih-Hung Chen

IPC: H01L21/306 ,  H01L29/792

CPC classification number: H01L29/7926 ,  H01L21/32139 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method for manufacturing semiconductor device is disclosed. A substrate with a conductive layer is provided, and a dummy layer is formed on the conductive layer. The dummy layer and at least a portion of the conductive layer are patterned to form several trenches. A first dielectric layer is formed to fill into the trenches so as to form several first dielectric elements in the trenches. The dummy layer is removed to expose parts of the first dielectric elements. A second dielectric layer is formed on the exposed parts of the first dielectric elements, and the second dielectric layer is patterned so that a spacer is formed at a lateral side of each exposed first dielectric element. The conductive layer is patterned by the spacers, so that a patterned conductive portion is formed at each lateral side of each first dielectric element.

Abstract translation: 公开了半导体器件的制造方法。 提供具有导电层的衬底，并且在导电层上形成虚设层。 虚拟层和导电层的至少一部分被图案化以形成几个沟槽。 形成第一电介质层以填充到沟槽中，以在沟槽中形成几个第一介电元件。 去除虚设层以露出第一电介质元件的部分。 在第一电介质元件的暴露部分上形成第二电介质层，并且图案化第二电介质层，使得在每个暴露的第一介电元件的侧面形成间隔物。 导电层通过间隔物图案化，使得在每个第一介电元件的每个横向侧上形成图案化的导电部分。

公开(公告)号：US20130161835A1

公开(公告)日：2013-06-27

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

公开(公告)号：US11960759B2

公开(公告)日：2024-04-16

申请号：US17851238

申请日：2022-06-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G06F12/00 ,  G06F3/06 ,  G06F16/9032

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F16/9032

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

公开(公告)号：US11800704B2

公开(公告)日：2023-10-24

申请号：US17009957

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H10B41/10 ,  H01L23/528 ,  H10B41/27

CPC classification number: H10B41/10 ,  H01L23/5283 ,  H10B41/27

Abstract: A memory device and a manufacturing method for the same are provided. The memory device includes a stacked body structure and a staircase structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The staircase structure is electrically connected to the stacked body structure. The staircase structure includes a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure includes a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

公开(公告)号：US11514300B2

公开(公告)日：2022-11-29

申请号：US16441065

申请日：2019-06-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G06N3/063 ,  H01C7/18 ,  H01L49/02 ,  G06N3/04

Abstract: A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

公开(公告)号：US11455534B2

公开(公告)日：2022-09-27

申请号：US16896942

申请日：2020-06-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G06N3/08 ,  G06N20/00 ,  G06N3/04 ,  G06K9/00 ,  G06K9/62

Abstract: A technology for cleaning a training data set for a neural network using dirty training data starts by accessing a labeled training data set that includes relatively dirty labeled data elements. The labeled training data set is divided into a first subset A and a second subset B. The procedure includes cycling between the subsets A and B, including producing refined model-filtered subsets of subsets A and B to provide a cleaned data set. Each refined model-filtered subset can have improved cleanliness and increased numbers of elements.

公开(公告)号：US11233049B2

公开(公告)日：2022-01-25

申请号：US16441097

申请日：2019-06-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/088 ,  H01L29/417 ,  G06N3/04 ,  G06N3/063 ,  H01L23/522

Abstract: A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

公开(公告)号：US20190326218A1

公开(公告)日：2019-10-24

申请号：US15960106

申请日：2018-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

公开(公告)号：US10332903B2

公开(公告)日：2019-06-25

申请号：US15382969

申请日：2016-12-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L21/768 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.