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    PATTERNING METHOD AND SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    PATTERNING METHOD AND SEMICONDUCTOR STRUCTURE 有权
    方法和半导体结构

    公开(公告)号：US20160189977A1

    公开(公告)日：2016-06-30

    申请号：US14582924

    申请日：2014-12-24

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/32139 ,  H01L21/0338

    Abstract: A patterning method and a patterned material layer are provided. After providing a substrate including a material layer, a hard mask layer including trenches extending in a first direction is formed over the material layer. A filling material layer is formed on the hard mask layer to cover the hard mask layer and fills in the trenches. A mask layer in a grid pattern is formed on the filling material layer. The mask layer includes first grid lines extending in the first direction and second grid lines extending in a second direction, and each of the underlying trench is located between two most adjacent first grid lines. The material layer is etched with the mask layer as an etching mask to form a patterned material layer including a plurality of first holes and a plurality of second holes.

    Abstract translation: 提供了图案化方法和图案化材料层。 在提供包括材料层的基板之后，在材料层上形成包括沿第一方向延伸的沟槽的硬掩模层。 在硬掩模层上形成填充材料层以覆盖硬掩模层并填充在沟槽中。 在填充材料层上形成网格图案的掩模层。 掩模层包括沿第一方向延伸的第一栅格线和沿第二方向延伸的第二栅格线，并且每个下面的沟槽位于两个最相邻的第一栅格线之间。 用掩模层作为蚀刻掩模蚀刻材料层以形成包括多个第一孔和多个第二孔的图案化材料层。

    Semiconductor device and method for fabricating the same
    5.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09343477B2

    公开(公告)日：2016-05-17

    申请号：US14478626

    申请日：2014-09-05

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575

    Abstract: Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar.

    Abstract translation: 提供了包括基板和堆叠层的半导体器件。 衬底包括第一区域，第二区域和第三区域。 第三区域设置在第一区域和第二区域之间。 由于第一区域中的基板的顶表面比第二区域中的基板的顶表面低，所以第三区域中的基板具有第一台阶高度。 堆叠层在第一和第三区域中设置在基板上。 第一区域中的堆叠层的顶表面和第二区域中的第三区域和衬底的顶表面基本上共面。

    METHOD FOR FORMING AN ALIGNED MASK
    8.
    发明申请
    METHOD FOR FORMING AN ALIGNED MASK 审中-公开

    公开(公告)号：US20190146330A1

    公开(公告)日：2019-05-16

    申请号：US15810551

    申请日：2017-11-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Cheng Yang

    IPC: G03F1/42 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  G03F1/80 ,  G03F1/76

    Abstract: A method for forming an aligned mask comprises etching a reference mark on a substrate to demarcate a boundary of an etch region; forming an etch mask on the substrate, using an exposure setting, the etch mask having a boundary; and measuring a distance between the reference mark and the boundary. When the measured distance is outside a margin of a target distance, then the etch mask is removed from the substrate, the exposure setting is changed, a next etch mask is formed using the changed exposure setting, and said measuring is repeated. A set of reference marks can be etched on a top level in a set of levels to demarcate boundaries of etch regions. An etch-trim process can be performed to form steps in the set of levels, wherein the etch-trim process includes at least first and second etch-trim cycles using first and second reference marks.

    Interconnect structure and fabricating method thereof
    10.
    发明授权
    Interconnect structure and fabricating method thereof 有权

    公开(公告)号：US10153233B1

    公开(公告)日：2018-12-11

    申请号：US15655596

    申请日：2017-07-20

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chi-Hao Huang ,  Chin-Cheng Yang

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.

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