公开(公告)号：US12002531B2

公开(公告)日：2024-06-04

申请号：US17648396

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US11983423B2

公开(公告)日：2024-05-14

申请号：US17648399

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F3/0634 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US11934252B2

公开(公告)日：2024-03-19

申请号：US17648394

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US20240078031A1

公开(公告)日：2024-03-07

申请号：US17929966

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Xing Wang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for dividing blocks for special functions are described. Some memory systems may be configured to assign a block of the memory system as a special function block configured with a first portion for storing information associated with a first function of the memory system and a second portion for storing information associated with a second function of the memory system; write a first set of information to the first portion of the block based at least in part on assigning the block as the special function block, the first set of information associated with the first function of the memory system; and write a second set of information to the second portion of the block based at least in part on assigning the block as the special function block, the second set of information associated with the second function of the memory system.

公开(公告)号：US11829613B2

公开(公告)日：2023-11-28

申请号：US17959844

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method includes receiving, by a processing device, signaling indicative of a power cycle (PC) to a memory device (MD) having a first signal indicative of a Power On Operation and a second signal indicative of a Power Off Operation, and determining an Average Power On Time (APOT) of the MD based, at least in part, on a quantity of power cycles (n) to the MD over a predetermined time interval (PTI), and for each PC over the PTI, an amount of time between receipt of the first signal and the second signal. A sum of each of the amount of time between receipt of the first signal and the second signal in the PTI provides a total power on time (T) to the MD, and the APOT is equal to T/n. When the APOT is less than (

公开(公告)号：US11720253B2

公开(公告)日：2023-08-08

申请号：US17646413

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Jun Huang ,  Bhagyashree Bokade ,  Violet Gomm ,  Deping He ,  Lavanya Sriram

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for access of a memory system based on fragmentation are described. The memory system may receive a first message indicating a set of data that the memory system is to store using a fragmentation-based write procedure. The memory system may, based on the first message, determine blocks of a memory device that satisfy a fragmentation threshold. After determining the blocks, the memory system may transmit to the host system a second message that indicates the memory system is ready to receive the set of data indicated in the first message. The memory system may then store the set of data in the determined blocks based on transmitting the second message.

公开(公告)号：US11714563B2

公开(公告)日：2023-08-01

申请号：US17574044

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0632 ,  G06F3/0653 ,  G06F3/0673

Abstract: Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.

公开(公告)号：US20230236986A1

公开(公告)日：2023-07-27

申请号：US18095782

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/1044 ,  G06F2212/6012

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US20230049201A1

公开(公告)日：2023-02-16

申请号：US17648396

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/20 ,  G06F11/07

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20230045990A1

公开(公告)日：2023-02-16

申请号：US17574059

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Chun Sum Yeung ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.