利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

120 条记录 (耗时 0.044 秒)

    System, method and computer program product for translating storage elements
    81.
    发明授权
    System, method and computer program product for translating storage elements 有权
    用于翻译存储元件的系统，方法和计算机程序产品

    公开(公告)号：US07966474B2

    公开(公告)日：2011-06-21

    申请号：US12036520

    申请日：2008-02-25

    申请人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

    发明人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

    IPC分类号： G06F9/26

    CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/355

    摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

    摘要翻译： 一种用于计算机系统中的翻译的系统，方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。 该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

    PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TOD CLOCKS
    82.
    发明申请
    PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TOD CLOCKS 有权
    执行同步时钟功能的功能指令

    公开(公告)号：US20090300401A1

    公开(公告)日：2009-12-03

    申请号：US12540261

    申请日：2009-08-12

    申请人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, SR.

    发明人： Eberhard Engler ,  Mark S. Farrell ,  Klaus Meissner ,  Ronald M. Smith, SR.

    IPC分类号： G06F1/12

    CPC分类号： G06F1/14

    摘要： A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function.

    摘要翻译： 一种用于执行用于使TOD时钟与其他计算机系统的TOD时钟同步的计算机系统的时间（TOD）时钟的执行定时设备（PTFF）指令的系统，方法和计算机程序产品。 计算机系统包括存储器; 以及与计算机存储器通信的处理器。 处理器能够执行PTFF指令，包括：获得在第一通用寄存器中指定的功能代码，用于识别要执行的查询功能或控制功能中的任何一个的功能代码; 从第二通用寄存器获取参数块的存储器地址; 响应于指定查询功能的功能代码，根据指定的查询功能将计算机系统的定时信息存储在参数块中; 响应于指定控制功能的功能代码，使用从参数块获得的定时信息来执行指定的控制功能; 并设置指示指定功能的结果的条件代码值。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS
    83.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS 有权
    方法，系统和计算机程序产品用于MILLICODE STORE ACCESS CHECKING说明

    公开(公告)号：US20090210680A1

    公开(公告)日：2009-08-20

    申请号：US12031756

    申请日：2008-02-15

    申请人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

    发明人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3861

    摘要： A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. The system further includes an execution unit to execute the millicode instruction. The execution unit performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.

    摘要翻译： 提供了一种用于毫存储存储访问检查指令的系统，方法和计算机程序产品。 该系统包括一个操作数访问控制寄存器（OACR），包括一个测试修改器指示符。 该系统还包括用于获取和解码指令的指令单元子系统。 该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。 该系统还包括执行毫代码指令的执行单元。 执行单元执行方法。 该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。

    Method and system for managing the result from a translator co-processor in a pipelined processor
    84.
    发明授权
    Method and system for managing the result from a translator co-processor in a pipelined processor 有权
    用于管理流水线处理器中的翻译协处理器的结果的方法和系统

    公开(公告)号：US06671793B1

    公开(公告)日：2003-12-30

    申请号：US09678061

    申请日：2000-10-02

    申请人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    发明人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    IPC分类号： G06F1516

    CPC分类号： G06F9/3017 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3879

    摘要： An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechanism allows the recovery unit to maintain the correct perform translator operation result with speculative execution and instruction level retry recovery throughout the duration of the perform translator operation.

    摘要翻译： 本发明的示例性实施例是用于管理从翻译器协处理器返回到中央处理器的恢复单元的结果的方法和系统。 计算机系统具有流水线计算机处理器和流水线中央处理器，其执行硬件控制执行单元中的指令集，并且在硬模式执行单元中以毫列指令序列执行毫模式架构状态指令集。 中央处理器在解码执行转换器操作指令之后的一个循环中向转译器协处理器发出一个请求。 翻译协处理器处理执行翻译器操作指令以产生执行转换器操作结果。 翻译协处理器将结果返回到中央处理器的恢复单元。 恢复单元将执行转换器操作结果存储在系统寄存器中。 由中央处理器执行的执行转换器操作结果的请求由恢复单元的硬件互锁互锁，直到转换器协处理器返回执行转换器操作结果。 该机制允许恢复单元在执行转换器操作的整个持续时间内通过推测执行和指令级重试恢复来维持正确的执行转换器操作结果。

    Specialized millicode instruction for range checking
    85.
    发明授权
    Specialized millicode instruction for range checking 失效
    专用millicode指令进行范围检查

    公开(公告)号：US5621909A

    公开(公告)日：1997-04-15

    申请号：US614148

    申请日：1996-03-12

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/00

    CPC分类号： G06F9/30021 ,  G06F9/30094

    摘要： A range check instruction sequence, which performs a logical comparison between two 32-bit values and updates the condition code as a result. It operates identically to the ESA/390 instruction compare logical (CLR) except for the way in which the condition code is set. The new condition code is a function of both the comparison result and the previous condition code. If the first operand is greater than the second operand, the condition code remains unchanged. If the first operand is less than or equal to the second operand, the condition code is set to 2 if it was previously 0 or 1, and is set to 3 if it was previously 2 or 3. This may be understood as advancing the state of the condition code among the groups (0,1), 2, and 3 if the first operand is not greater than the second operand.

    摘要翻译： 范围检查指令序列，其执行两个32位值之间的逻辑比较，并作为结果更新条件代码。 除了条件码的设置方式以外，它与ESA / 390指令比较逻辑（CLR）相同。 新条件代码是比较结果和先前条件代码的函数。 如果第一个操作数大于第二个操作数，则条件代码保持不变。 如果第一个操作数小于或等于第二个操作数，则如果先前为0或1，则条件代码设置为2，如果先前为2或3，则将其设置为3。这可以被理解为推进状态 如果第一个操作数不大于第二个操作数，组（0,1），2和3中的条件代码。

    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system
    88.
    发明授权
    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
    微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取

    公开(公告)号：US08549255B2

    公开(公告)日：2013-10-01

    申请号：US12032041

    申请日：2008-02-15

    申请人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30047 ,  G06F12/0862

    摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.

    摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访​​问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。