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81.发明授权Apparatus and method of performing screen to screen blits in a color sliced frame buffer architecture 失效在彩色切片帧缓冲器架构中执行屏幕屏幕截图的装置和方法
公开(公告)号：US6061069A
公开(公告)日：2000-05-09
申请号：US687854
申请日：1996-07-26
CPC分类号： G06T1/20
摘要： A method and apparatus for moving pixel data from one area of a frame buffer to another in block fashion are provided. In one embodiment of the invention, pixel data is decomposed into its RGB component and each RGB component is stored into the frame buffer in a particular memory bank. The pixel data is moved by moving all the components of the data stored in a memory bank before moving the components in other memory banks.
摘要翻译： 提供了一种用于以帧的方式将像素数据从帧缓冲器的一个区域移动到另一个区域的方法和装置。 在本发明的一个实施例中，像素数据被分解为其RGB分量，并且每个RGB分量被存储在特定存储体中的帧缓冲器中。 在移动其他存储体中的组件之前，通过移动存储在存储体中的数据的所有分量来移动像素数据。
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公开(公告)号：US09097590B2
公开(公告)日：2015-08-04
申请号：US12916922
申请日：2010-11-01
摘要： A data processing system and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.
摘要翻译： 提供了一种数据处理系统和处理器，用于通过性能监视跟踪热数据。 性能监视器设置为跟踪模式。 温度由数字热传感器在一段时间内感测到。 感测到的温度被存储在数据结构中，并且图形地显示感测到的温度的痕迹。
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公开(公告)号：US08838950B2
公开(公告)日：2014-09-16
申请号：US10601374
申请日：2003-06-23
申请人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译： 本发明提供了验证代码和/或数据并提供受保护的环境以供执行。 本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。 本地商店被划分成一个隔离和非隔离的部分。 代码或数据被加载到隔离的部分。 代码或数据在本地存储的隔离部分进行身份验证。 认证后，执行代码。 在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。
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84.发明授权Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set 失效在可选数量的监视终端和处理第二组时，停止对第一组循环的并行处理公开(公告)号：US08683185B2
公开(公告)日：2014-03-25
申请号：US12843224
申请日：2010-07-26
申请人： Brian Flachs , Charles Ray Johns , Ulrich Weigand
发明人： Brian Flachs , Charles Ray Johns , Ulrich Weigand
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F8/452 , G06F9/30065 , G06F9/30076 , G06F9/3806 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3853 , G06F9/3857
摘要： The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.
摘要翻译： 示例性实施例包括具有用于处理具有循环的指令的处理器单元的方法，数据处理系统和计算机程序产品。 处理器单元创建具有第一组循环和第二组指令的第一组指令，其具有来自指令的第二组循环。 第一组循环与第二组循环具有不同的并行处理顺序。 处理器单元处理第一组。 处理器单元在第一组处理期间监视第一组回路中的终端。 处理器单元确定在第一组环路中正在监视的终端数量是否大于可选数量的终端。 响应于确定终端的数量大于可选择的终端数量，处理器单元停止处理第一组并处理第二组。
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85.发明授权Methods and apparatus for reducing command processing latency while maintaining coherence 失效减少命令处理延迟同时保持一致性的方法和装置公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。
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86.发明授权Support of deep power savings mode and partial good in a thermal management system 失效支持深度节电模式和部分良好的热管理系统公开(公告)号：US07957848B2
公开(公告)日：2011-06-07
申请号：US12264660
申请日：2008-11-04
CPC分类号： G06F1/3203 , G01K3/005 , G01K7/015 , G06F1/206 , Y02D10/16
摘要： A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.
摘要翻译： 提供计算机实现的方法，数据处理系统和处理器来管理热管理系统。 确定多个数字热传感器是否有故障或功能。 响应于所述多个数字热传感器中的至少一个正在起作用，来监视与功能数字热传感器相关联的集成电路内的至少一个单元的功率节省模式。 响应于至少一个单元处于省电模式，功能数字热传感器被禁用。
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公开(公告)号：US20110040517A1
公开(公告)日：2011-02-17
申请号：US12916922
申请日：2010-11-01
摘要： A data processing system and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.
摘要翻译： 提供了一种数据处理系统和处理器，用于通过性能监视跟踪热数据。 性能监视器设置为跟踪模式。 温度由数字热传感器在一段时间内感测到。 感测到的温度被存储在数据结构中，并且图形地显示感测到的温度的痕迹。
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公开(公告)号：US07848901B2
公开(公告)日：2010-12-07
申请号：US12244596
申请日：2008-10-02
IPC分类号： G01K1/00
摘要： A computer implemented method, data processing system, and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.
摘要翻译： 提供计算机实现的方法，数据处理系统和处理器，用于通过性能监视跟踪热数据。 性能监视器设置为跟踪模式。 温度由数字热传感器在一段时间内感测到。 感测到的温度被存储在数据结构中，并且图形地显示感测到的温度的痕迹。
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89.发明授权Method and apparatus for power throttling a processor in an information handling system 有权用于在信息处理系统中对处理器进行功率调节的方法和装置公开(公告)号：US07793125B2
公开(公告)日：2010-09-07
申请号：US11621710
申请日：2007-01-10
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/266 , G06F1/329 , G06F1/3296 , G06F9/3836 , G06F9/3869 , G06F9/3891 , Y02D10/172 , Y02D10/24 , Y02D50/20
摘要： A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.
摘要翻译： 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率超过预定阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速率，以提供功率节流。 与期望的输出电压相比，电力系统动态响应处理器电路从电力系统接收的实际输出电压的变化，并对这种变化进行校正。
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公开(公告)号：US07756668B2
公开(公告)日：2010-07-13
申请号：US12117028
申请日：2008-05-08
IPC分类号： G01K1/00
摘要： A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal sensor is read and a determination is made as to whether the sensed temperature is higher than a current maximal temperature. The sensed temperature is logged in response to the sensed temperature being higher than the current maximal temperature. The sensed temperature becomes a new maximal temperature for the integrated circuit.
摘要翻译： 提供计算机实现的方法，数据处理系统和处理器用于记录集成电路中的最大温度。 数字热传感器感测集成电路中的温度。 读取感测到的数字热传感器的温度，并确定所感测的温度是否高于当前的最大温度。 响应于所感测的温度高于当前最大温度来记录检测到的温度。 感测的温度成为集成电路的新的最高温度。
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