公开(公告)号：US20110241725A1

公开(公告)日：2011-10-06

申请号：US13052400

申请日：2011-03-21

申请人： Yoshifumi IKENAGA ,  Masahiro Nomura

发明人： Yoshifumi IKENAGA ,  Masahiro Nomura

IPC分类号： H03K19/00 ,  G01R25/00

CPC分类号： H03K19/00392

摘要： When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

摘要翻译： 当监视电路中指定的一个监视器电路的操作有故障或每个监视器电路中形成环形振荡器的元件中的任何元件具有特征异常时，如果基于监视器以最低速度操作的结果执行电压控制，则所需的 电压可能被高估了。 这导致功耗的增加，并且当计算来自多个监视器的检测结果的平均值时，也导致精度降低。 提供多个监视器电路。 在其检测结果中，忽略超出预定范围的任何检测结果，并且将剩余监视结果的平均值用作最终监视检测值。

公开(公告)号：US08004348B2

公开(公告)日：2011-08-23

申请号：US12526988

申请日：2008-02-14

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： G05F1/10

CPC分类号： H03K19/00384

摘要： A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.

摘要翻译： 控制电路控制电源电压馈电电路，并控制馈送到目标电路的电源电压。 参考速度监视器监视目标电路中的关键路径的延迟时间是否满足所需的操作速度。 电压差监视器监视目标电路的电源电压与目标电路的阈值电压之间的差异，以输出电压差信息。 控制电路根据基准速度监视器的监视结果来决定是否增加或减小电源电压。 控制电路确定电源电压的变化率，使得电源电压的控制速率与从电压差监视器输出的电压差信息成比例。

公开(公告)号：US07960035B2

公开(公告)日：2011-06-14

申请号：US11909724

申请日：2006-03-30

申请人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

发明人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

IPC分类号： B32B3/00 ,  B32B5/00 ,  B32B15/00 ,  B32B15/18 ,  B32B15/20

CPC分类号： C21D9/46 ,  C22C38/00 ,  C22C38/06 ,  C22C38/58 ,  C23C22/12 ,  C23G1/08 ,  Y10T428/12979 ,  Y10T428/12993 ,  Y10T428/26

摘要： There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 μm, and an average interval (Sm) of the pits and the bumps is not more than 30 μm, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength.

摘要翻译： 提供了优异的磷酸化性的高强度热轧钢板，其中存在于其表面上的凹坑和凸块的最大深度（Ry）不小于10μm，并且凹坑的平均间隔（Sm） 并且凸起不大于30μm，满足对凹坑的负载长度比（tp40）和表面上的凸块的要求不大于20％，或者要求负载长度比（ tp60）和负载长度比（tp40），不小于60％，或其两者。 高强度热轧钢板即使在强度高的情况下也能够高效地加强强化，能够表现出稳定且优异的磷酸化性。

公开(公告)号：US07830703B2

公开(公告)日：2010-11-09

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20100117705A1

公开(公告)日：2010-05-13

申请号：US12588993

申请日：2009-11-04

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/26

摘要： A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

摘要翻译： 多个延迟路径并联连接在与时钟信号CLK同步操作的两个同步操作电路之间，并且使能信号的传输。 延迟检测单元检测多个延迟路径的各个延迟时间，并且控制单元基于来自延迟检测单元的检测结果从多个延迟路径中选择一个延迟路径，并且控制信号传输阻塞 除了所选择的一个延迟路径之外的延迟路径。

公开(公告)号：US20100033235A1

公开(公告)日：2010-02-11

申请号：US12526988

申请日：2008-02-14

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： G05F1/10

CPC分类号： H03K19/00384

摘要： A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.

摘要翻译： 控制电路控制电源电压馈电电路，并控制馈送到目标电路的电源电压。 参考速度监视器监视目标电路中的关键路径的延迟时间是否满足所需的操作速度。 电压差监视器监视目标电路的电源电压与目标电路的阈值电压之间的差异，以输出电压差信息。 控制电路根据基准速度监视器的监视结果来决定是否增加或减小电源电压。 控制电路确定电源电压的变化率，使得电源电压的控制速率与从电压差监视器输出的电压差信息成比例。

公开(公告)号：US20090201063A1

公开(公告)日：2009-08-13

申请号：US12160071

申请日：2006-12-28

申请人： Masahiro Nomura ,  Yoshifumi Ikenaga ,  Koichi Takeda

发明人： Masahiro Nomura ,  Yoshifumi Ikenaga ,  Koichi Takeda

IPC分类号： H03K3/289

CPC分类号： H03K3/35625 ,  H03K19/096

摘要： A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased.

摘要翻译： 动态半导体器件具有多个具有用于临时存储输入数据和动态门部分的开关部分的主步进部分; 多个从步骤部分，与主阶段部分交替地连接并设置有动态门部分或者具有锁存部分和动态门部分; 以及定时信号产生部分，用于产生用于控制主步进部分和从步进部分的操作的信号。 定时信号生成部分在锁存部分提供用于存储数据被擦除之前的前一步骤的数据的信号。

公开(公告)号：US20090014095A1

公开(公告)日：2009-01-15

申请号：US12162878

申请日：2007-03-29

申请人： Yoichi Mukai ,  Shinji Kozuma ,  Masahiro Nomura

发明人： Yoichi Mukai ,  Shinji Kozuma ,  Masahiro Nomura

IPC分类号： C22C38/00 ,  B32B3/00

CPC分类号： C21D9/46 ,  C22C38/02 ,  C22C38/04 ,  C22C38/06 ,  Y10T428/12993

摘要： The invention provides a high strength cold rolled steel sheet having excellent chemical conversion treatment property stably even Mo is added aiming high strengthening. The surface property of the cold rolled steel sheet satisfies that the characteristic of 10 μm or more of the maximum depth (Ry) of the unevenness and 30 μm or less of the average spacing (Sm) of the unevenness, and that either one or more preferably both of, the characteristic of the load length ratio (tp40) of the unevenness of the surface is 20% or less, and the characteristic of the difference of the load length ratios (tp60) and (tp40) is 60% or more, is satisfied, and the crack of 3 μm or less width and 5 μm or more depth does not exist on the surface.

摘要翻译： 本发明提供了一种具有优异的化学转化处理性能的高强度冷轧钢板，即使添加Mo以达到高强度。 冷轧钢板的表面特性满足不平坦部的最大深度（Ry）为10μm以上，凹凸的平均间隔（Sm）为30μm以下的特性，以及任一个或多个 优选地，表面的不平坦度的负载长度比（tp40）的特性都为20％以下，负载长度比（tp60）和（tp40）的差的特性为60％以上， 满意，表面上不存在3μm以下的宽度和5μm以上的深度的裂纹。

公开(公告)号：US20080251849A1

公开(公告)日：2008-10-16

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US07425860B2

公开(公告)日：2008-09-16

申请号：US10533304

申请日：2003-10-30

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

摘要翻译： 当控制第一电源时，降低短路电流和延迟增加的电平移位器。 在用于将提供第一电源的第一逻辑电路的信号电平转换为提供第二电源的第二逻辑电路的信号电平的电平移位器中，所述电路包括在GND电源 电平移位核心电路的源极端子和GND电源。 开关电路由在第一电源的控制下产生控制信号的第三逻辑电路和在电平移位核心电路的输出端的上拉/下拉电路来控制。 上拉和/或下拉电路由第三逻辑电路控制。