Method to control mechanical stress of copper interconnect line using post-plating copper anneal
    81.
    发明授权
    Method to control mechanical stress of copper interconnect line using post-plating copper anneal 有权
    使用后镀铜退火来控制铜互连线的机械应力的方法

    公开(公告)号:US06368967B1

    公开(公告)日:2002-04-09

    申请号:US09564610

    申请日:2000-05-04

    申请人: Paul R. Besser

    发明人: Paul R. Besser

    IPC分类号: H01L2144

    摘要: A method is provided, the method comprising forming a first dielectric layer above a first structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure above the first dielectric layer and in the first opening. The method also comprises annealing the first copper structure using one of a furnace anneal process performed at a temperature ranging from approximately 100-400° C. for a time ranging from approximately 10-90 minutes and a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 100-400° C. for a time ranging from approximately 10-180 seconds.

    摘要翻译: 提供了一种方法,所述方法包括在第一结构层上形成第一介电层,在第一介电层中形成第一开口,以及在第一介电层上方和第一开口中形成第一铜结构。 该方法还包括使用在大约100-400℃的温度范围内进行的炉退火处理之一,时间范围为大约10-90分钟和在快速热退火(RTA)工艺 温度范围为约100-400℃,时间范围为约10-180秒。

    Method of forming a semiconductor device with metal silicide regions
    82.
    发明授权
    Method of forming a semiconductor device with metal silicide regions 有权
    用金属硅化物区形成半导体器件的方法

    公开(公告)号:US06268255B1

    公开(公告)日:2001-07-31

    申请号:US09479402

    申请日:2000-01-06

    IPC分类号: H01L21336

    摘要: The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.

    摘要翻译: 本发明涉及制造半导体器件的方法。 在一个说明性实施例中,该方法包括形成由多晶硅组成的第一层,在多晶硅层上形成由难熔金属组成的第二层,并将第二层的至少一部分转化为第一金属硅化物。 该方法还包括在难熔金属层或第一金属硅化物层之上形成抗反射涂层,以及对第一金属硅化物层和多晶硅层进行构图以限定由第一金属硅化物区和 多晶硅层,在衬底中形成多个源极/漏极区域,在至少栅极堆叠和源极/漏极区域上形成由难熔金属组成的第三层,并将第三层的至少一部分转化为 第二金属硅化物区域。

    Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
    83.
    发明授权
    Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions 有权
    通过源极和漏极区域的非晶化在半导体晶片中形成结漏电的金属硅化物的方法

    公开(公告)号:US06255214B1

    公开(公告)日:2001-07-03

    申请号:US09256782

    申请日:1999-02-24

    IPC分类号: H01L2144

    CPC分类号: H01L21/28518

    摘要: A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process amorphizes the semiconductor material in the gate and source/drain junctions prior to the deposition of the metal during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, non-dopant material, such as silicon or germanium, is implanted into the semiconductor material in an unmasked implantation procedure. This highly controllable implanting creates amorphous silicon regions with a substantially smooth interface with the crystalline silicon. When the silicide regions are formed during subsequent annealing steps, the silicide forms in a manner that follows the amorphous regions so that the silicide/silicon interface is also substantially smooth and junction leakage induced by silicidation is prevented.

    摘要翻译: 在半导体晶片中形成具有减小的由硅化工艺引起的结漏电的超浅结的方法使在硅化物中沉积金属之前的栅极和源极/漏极结中的半导体材料非晶化。 在半导体器件中形成栅极和源极/漏极结之后,在未掩模的注入工艺中将非掺杂材料(例如硅或锗)注入到半导体材料中。 这种高度可控制的植入产生具有与晶体硅基本平滑界面的非晶硅区域。 当在随后的退火步骤期间形成硅化物区域时,硅化物以非晶区域的方式形成,使得硅化物/硅界面也基本上是平滑的,并且防止了由硅化物引起的接合泄漏。

    Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
    84.
    发明授权
    Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines 失效
    降低半导体互连线中应力诱发空隙的发生率的方法

    公开(公告)号:US06221794B1

    公开(公告)日:2001-04-24

    申请号:US09208596

    申请日:1998-12-08

    IPC分类号: H01L2131

    摘要: In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During processing the deposition temperature is reduced to under 400 degrees Celsius, specifically temperatures in the range of about 350 degrees Celsius to about 380 degrees, Celsius, resulting in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

    摘要翻译: 在基板的微电路互连线上形成层间电介质(ILD)涂层的方法中,通过使用等离子体增强化学气相沉积形成SiON层。 使用由氮气,一氧化二氮和硅烷气体形成的等离子体的沉积,其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 在加工过程中,沉积温度降低至400摄氏度以下,特别是约350摄氏度至约380摄氏度的温度,导致底层互连线中应力引起的空隙的发生率基本上降低。 此外,在沉积期间,对沉积温度和工艺压力进行微调,以控制SiON层的光学特性。 测试SiON层的可接受的光学性能,并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD,底物就可以进行进一步的处理。

    Tensile strained substrate
    87.
    发明授权
    Tensile strained substrate 有权
    拉伸应变基材

    公开(公告)号:US07701019B2

    公开(公告)日:2010-04-20

    申请号:US11356606

    申请日:2006-02-17

    IPC分类号: H01L27/088

    摘要: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译: 示例性实施例涉及形成金属氧化物半导体场效应晶体管(MOSFET)的方法。 该方法包括提供一个衬底,该衬底具有形成在衬底上方的栅极,并且执行以下沉积步骤中的至少一个:在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物,栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层,沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Ultra-uniform silicide system in integrated circuit technology
    89.
    发明授权
    Ultra-uniform silicide system in integrated circuit technology 有权
    集成电路技术中超均匀的硅化物系统

    公开(公告)号:US07307322B2

    公开(公告)日:2007-12-11

    申请号:US11252493

    申请日:2005-10-17

    IPC分类号: H01L29/76

    CPC分类号: H01L21/28518

    摘要: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

    摘要翻译: 提供集成电路的结构。 在半导体衬底上形成栅极电介质,并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物,并且在半导体衬底上沉积电介质层。 然后在介电层中形成与超均匀硅化物的接触。