中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

96 records (took 0.033 seconds)

    MAINTAINING QUEUES FOR MEMORY SUB-SYSTEMS
    82.
    发明申请
    MAINTAINING QUEUES FOR MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20220413719A1

    公开(公告)日：2022-12-29

    申请号：US16954272

    申请日：2020-03-10

    Applicant: Micron Technology, Inc.

    Inventor： Jiangang Wu ,  Jing Sang Liu ,  James P. Crowley ,  Yun Li

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for data stream processing for maintaining queues for memory sub-systems are described. A number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system can be determined. Each queue can be associated with a respective priority level and can be configured to maintain a respective set of commands. A command can be assigned to the queue based on a number of commands included in the queue. One or more commands can be issued from the queues based on the respective priority levels of the queues.

    MANAGING VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE
    84.
    发明申请
    MANAGING VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE 有权

    公开(公告)号：US20220317902A1

    公开(公告)日：2022-10-06

    申请号：US17219489

    申请日：2021-03-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D. Schuh ,  Jiangang Wu

    IPC: G06F3/06

    Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

    Granular error reporting on multi-pass programming of non-volatile memory
    85.
    发明授权
    Granular error reporting on multi-pass programming of non-volatile memory 有权

    公开(公告)号：US11461158B2

    公开(公告)日：2022-10-04

    申请号：US15733561

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Qisong Lin ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Shao Chun Shi

    IPC: G06F11/00 ,  G06F11/07

    Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.

    Memory sub-system logical block address remapping
    86.
    发明授权
    Memory sub-system logical block address remapping 有权

    公开(公告)号：US11416388B2

    公开(公告)日：2022-08-16

    申请号：US17027895

    申请日：2020-09-22

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jiangang Wu ,  Gil Golov

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0873 ,  G06F11/30 ,  G06F12/0811

    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

    AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT
    87.
    发明申请
    AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT 有权

    公开(公告)号：US20220236871A1

    公开(公告)日：2022-07-28

    申请号：US17160144

    申请日：2021-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

    IPC: G06F3/06

    Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

    MEMORY SUB-SYSTEM WRITE SEQUENCE TRACK
    88.
    发明申请
    MEMORY SUB-SYSTEM WRITE SEQUENCE TRACK 有权

    公开(公告)号：US20220188223A1

    公开(公告)日：2022-06-16

    申请号：US17536928

    申请日：2021-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Kishore K. Muchherla

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F3/06

    Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

Patent Agency Ranking