公开(公告)号：US11934689B2

公开(公告)日：2024-03-19

申请号：US17984929

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, Jr. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/0483

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US11715531B2

公开(公告)日：2023-08-01

申请号：US17210713

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Christopher M. Smitchger ,  Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C29/50

CPC classification number: G11C16/3418 ,  G11C16/105 ,  G11C16/26 ,  G11C29/50004

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

公开(公告)号：US11687452B2

公开(公告)日：2023-06-27

申请号：US17123244

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C16/04 ,  G06F12/06 ,  G06F1/28 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F12/0646 ,  G06F1/28 ,  G11C16/3459 ,  G06F2212/1028 ,  G11C16/10

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

公开(公告)号：US11507300B2

公开(公告)日：2022-11-22

申请号：US17080567

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, Jr. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC: G11C16/26 ,  G06F3/06 ,  G06F11/07 ,  G11C16/34 ,  G11C16/04

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US20220310183A1

公开(公告)日：2022-09-29

申请号：US17210713

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Christopher M. Smitchger ,  Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

公开(公告)号：US20220301640A1

公开(公告)日：2022-09-22

申请号：US17837816

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/52 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

公开(公告)号：US20220284974A1

公开(公告)日：2022-09-08

申请号：US17249448

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Michael G. Miller ,  Gary F. Besinga ,  Christopher M. Smitchger

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.

公开(公告)号：US20220129187A1

公开(公告)日：2022-04-28

申请号：US17080567

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, JR. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US20220091740A1

公开(公告)日：2022-03-24

申请号：US17457615

申请日：2021-12-03

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath k. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0888 ,  G06F11/34 ,  G06F12/0893

Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.

公开(公告)号：US20220013182A1

公开(公告)日：2022-01-13

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.