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公开(公告)号:US20210241823A1
公开(公告)日:2021-08-05
申请号:US17238846
申请日:2021-04-23
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号: G11C11/406 , G06F13/16 , G11C7/04
摘要: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
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公开(公告)号:US20200159447A1
公开(公告)日:2020-05-21
申请号:US16193171
申请日:2018-11-16
发明人: Ting Luo , Kishore Kumar Muchherla , Harish Reddy Singidi , Xiangang Luo , Renato Padilla, JR. , Gary F. Besinga , Sampath Ratnam , Vamsi Pavan Rayaprolu
摘要: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.
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公开(公告)号:US20220188040A1
公开(公告)日:2022-06-16
申请号:US17685102
申请日:2022-03-02
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号:US20200278814A1
公开(公告)日:2020-09-03
申请号:US16878304
申请日:2020-05-19
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号:US20200004465A1
公开(公告)日:2020-01-02
申请号:US16566545
申请日:2019-09-10
发明人: Michael G. Miller , Kishore Kumar Muchherla , Harish Reddy Singidi , Sampath Ratnam , Renato Padilla, JR. , Gary F. Besinga , Peter Sean Feeley
摘要: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
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公开(公告)号:US20200251162A1
公开(公告)日:2020-08-06
申请号:US16855579
申请日:2020-04-22
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号: G11C11/406 , G06F13/16
摘要: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
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公开(公告)号:US20200098421A1
公开(公告)日:2020-03-26
申请号:US16138115
申请日:2018-09-21
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号: G11C11/406 , G06F13/16
摘要: Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.
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公开(公告)号:US20200097211A1
公开(公告)日:2020-03-26
申请号:US16138334
申请日:2018-09-21
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号:US20230076362A1
公开(公告)日:2023-03-09
申请号:US17984929
申请日:2022-11-10
发明人: Michael G. Miller , Ashutosh Malshe , Gianni Stephen Alsasua , Renato Padilla, JR. , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Harish Reddy Singidi
摘要: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
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公开(公告)号:US20200319827A1
公开(公告)日:2020-10-08
申请号:US16909503
申请日:2020-06-23
发明人: Gianni Stephen Alsasua , Karl D. Schuh , Ashutosh Malshe , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Sampath Ratnam , Harish Reddy Singidi , Renato Padilla, JR.
IPC分类号: G06F3/06 , G06F12/1009 , G11C16/34 , G11C16/26
摘要: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
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