公开(公告)号：US11175979B2

公开(公告)日：2021-11-16

申请号：US16533328

申请日：2019-08-06

申请人： MICRON TECHNOLOGY, INC.

发明人： Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Xiangang Luo

IPC分类号： G06F11/07

摘要： A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.

公开(公告)号：US11158392B2

公开(公告)日：2021-10-26

申请号：US16412879

申请日：2019-05-15

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC分类号： G11C16/34

摘要： Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11157400B2

公开(公告)日：2021-10-26

申请号：US16737662

申请日：2020-01-08

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0871

摘要： A garbage collection operation can be performed on one or more data blocks of a memory sub-system, where data is stored at the one or more data blocks using a first write mode. In response to determining that the garbage collection operation satisfies a performance condition, a determination is made as to whether a data block of a cache area of the memory sub-system satisfies an endurance condition, where data is stored at the data block of the cache area using a second write mode. A write mode for the data block of the cache area is changed from the second write mode to the first write mode responsive to determining that the data block satisfies the endurance condition. The data block of the cache area is then used in the garbage collection operation.

公开(公告)号：US11106577B2

公开(公告)日：2021-08-31

申请号：US16175005

申请日：2018-10-30

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale

IPC分类号： G06F12/128 ,  G06F12/02 ,  G06F12/0897

摘要： An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.

公开(公告)号：US20210241823A1

公开(公告)日：2021-08-05

申请号：US17238846

申请日：2021-04-23

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, JR.

IPC分类号： G11C11/406 ,  G06F13/16 ,  G11C7/04

摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US20210191858A1

公开(公告)日：2021-06-24

申请号：US17196934

申请日：2021-03-09

申请人： Micron Technology, Inc.

发明人： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC分类号： G06F12/02 ,  G06F12/0891

摘要： Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.

公开(公告)号：US10998034B2

公开(公告)日：2021-05-04

申请号：US17017201

申请日：2020-09-10

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC分类号： G11C7/04 ,  G11C11/406 ,  G06F13/16

摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US20210117318A1

公开(公告)日：2021-04-22

申请号：US17247805

申请日：2020-12-23

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Peter Sean Feeley

IPC分类号： G06F12/02

摘要： A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.

公开(公告)号：US10915444B2

公开(公告)日：2021-02-09

申请号：US16234271

申请日：2018-12-27

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Peter Sean Feeley

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/02

摘要： A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion. Responsive to the rate of change satisfying the third threshold criterion, the processing device identifies the first data block as a candidate for garbage collection on the memory component.

公开(公告)号：US20210027846A1

公开(公告)日：2021-01-28

申请号：US17035149

申请日：2020-09-28

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC分类号： G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.