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    APPARATUSES AND METHODS FOR REDUCING CURRENT LEAKAGE IN A MEMORY
    81.
    发明申请
    APPARATUSES AND METHODS FOR REDUCING CURRENT LEAKAGE IN A MEMORY 有权
    用于减少存储器中的电流泄漏的装置和方法

    公开(公告)号：US20150049565A1

    公开(公告)日：2015-02-19

    申请号：US13970518

    申请日：2013-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Zhong-yi Xia ,  Scott J. Derner ,  Charles L. Ingalls ,  Howard C. Kirsch

    IPC: G11C7/06 ,  G11C7/12

    CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C16/28

    Abstract: Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

    Abstract translation: 描述了用于在存储器中操作读出放大器电路的装置，读出放大器电路和方法。 示例性装置包括读出放大器电路，其被配置为耦合到数字线并且被配置为在存储器访问操作期间将数字线驱动到指示由耦合到数字的存储器单元存储的电荷的逻辑值的电压 线。 在存储器访问操作的初始时间周期期间，读出放大器电路被配置为将数字线驱动到指示由存储器单元存储的电荷的逻辑值的第一电压。 在初始时间段之后，读出放大器电路被配置为将数字线驱动到不同于指示由存储器单元存储的电荷的逻辑值的第一电压的第二电压。

    METHOD AND APPARATUS FOR SENSING IN A MEMORY
    82.
    发明申请
    METHOD AND APPARATUS FOR SENSING IN A MEMORY 有权
    用于感知记忆的方法和装置

    公开(公告)号：US20150029781A1

    公开(公告)日：2015-01-29

    申请号：US13948951

    申请日：2013-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner

    IPC: G11C11/4091

    CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/08

    Abstract: A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data line for charge sharing. The activation device can then be disabled to isolate the memory cell capacitor from the active data line. The state of the memory cell can then be sensed while the memory cell capacitor is isolated from the active data line. After the sense operation, the activation device can be re-enabled in order to restore the data to the memory cell capacitor that was destroyed during the sense operation.

    Abstract translation: 描述了一种在存储单元电容器与数据线隔离的同时感测存储单元的状态的方法和存储器。 可以使存储器单元的激活装置能够将存储单元电容器耦合到有源数据线的寄生电容用于电荷共享。 然后可以禁用激活装置以将存储单元电容器与活动数据线隔离。 然后可以在存储单元电容器与有源数据线隔离的同时感测存储单元的状态。 在感测操作之后，可以重新启用激活装置，以便将数据恢复到在感测操作期间被破坏的存储单元电容器。

    Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices
    83.
    发明申请
    Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices 有权

    公开(公告)号：US20240431090A1

    公开(公告)日：2024-12-26

    申请号：US18821139

    申请日：2024-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78

    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

    Integrated memory comprising secondary access devices between digit lines and primary access devices
    87.
    发明授权
    Integrated memory comprising secondary access devices between digit lines and primary access devices 有权

    公开(公告)号：US11450668B2

    公开(公告)日：2022-09-20

    申请号：US17324976

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: G11C11/24 ,  H01L27/108 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4091

    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

    Half density ferroelectric memory and operation
    88.
    发明授权
    Half density ferroelectric memory and operation 有权

    公开(公告)号：US11250900B2

    公开(公告)日：2022-02-15

    申请号：US17001296

    申请日：2020-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: G11C11/22 ,  G11C7/06 ,  G11C7/00 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/16 ,  G11C11/56

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

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