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公开(公告)号：US20100033609A1
公开(公告)日：2010-02-11
申请号：US12473876
申请日：2009-05-28
申请人： Hiroshi KATO , Katsumi Dosaka , Fukashi Morishita
发明人： Hiroshi KATO , Katsumi Dosaka , Fukashi Morishita
IPC分类号： H04N5/335
CPC分类号： H04N5/3742 , H04N5/378
摘要： To obtain a solid state imaging device having a data transfer function capable of outputting digital data after A/D conversion to the outside in a high speed.Each of eight stage data blocks in a data bus part has a data line pair and an amplifier part which is coupled to the data line pair. Then, the amplifier part amplifies a signal of the data line pair on an amplifier data line pair to output the amplified signal as block data outputs at timing indicated by an amplifier enable signal and an amplifier control signal. Further, the eight stage data blocks are coupled with each other from the first stage to the last stage so that the preceding stage block data outputs may be provided to the following stage data line pair as block data inputs, respectively.
摘要翻译： 获得具有数据传送功能的固态成像装置，该数据传输功能能够在高速A / D转换到外部之后输出数字数据。 数据总线部分中的八级数据块中的每一个具有数据线对和耦合到数据线对的放大器部分。 然后，放大器部分放大放大器数据线对上的数据线对的信号，以在由放大器使能信号和放大器控制信号指示的定时处输出放大信号作为块数据输出。 此外，八级数据块从第一级到最后级彼此耦合，使得前级级块数据输出可以分别作为块数据输入提供给后级数据线对。
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公开(公告)号：US20090058543A1
公开(公告)日：2009-03-05
申请号：US12289230
申请日：2008-10-23
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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公开(公告)号：US07459983B2
公开(公告)日：2008-12-02
申请号：US11452317
申请日：2006-06-14
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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84.发明授权Internal voltage generating circuit and semiconductor integrated circuit device 有权内部电压发生电路和半导体集成电路器件公开(公告)号：US07456680B2
公开(公告)日：2008-11-25
申请号：US11135488
申请日：2005-05-24
CPC分类号： G05F1/465
摘要： A voltage for reference at a voltage level higher than a target value is produced from a constant current provided from a constant current generating circuit, and is subjected to resistance division by a resistance division circuit to produce a reference voltage at the target level, and then a final reference voltage is produced by a voltage follower. An internal voltage generating circuit thus provided can generate the reference voltage having the desired voltage level with high accuracy as well as an internal voltage based on the reference voltage by controlling temperature characteristic even with a low power supply voltage.
摘要翻译： 在从恒定电流产生电路提供的恒定电流中产生高于目标值的电压电压的参考电压，并通过电阻分割电路进行电阻分割以产生目标电平的参考电压，然后 最终的参考电压由电压跟随器产生。 由此提供的内部电压产生电路即使在低电源电压下也可以通过控制温度特性，以高精度产生具有所需电压电平的基准电压以及基于参考电压的内部电压。
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公开(公告)号：US20070263466A1
公开(公告)日：2007-11-15
申请号：US11797804
申请日：2007-05-08
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/065 , G11C7/08 , G11C7/1048 , G11C11/405 , G11C11/4091 , G11C11/4099 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/10897 , H01L27/1203 , H01L29/7841
摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).
摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。
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86.发明申请Internal voltage generating circuit and semiconductor integrated circuit device 审中-公开内部电压发生电路和半导体集成电路器件公开(公告)号：US20070262812A1
公开(公告)日：2007-11-15
申请号：US11826164
申请日：2007-07-12
IPC分类号： G05F3/02
CPC分类号： G05F1/465
摘要： A voltage for reference at a voltage level higher than a target value is produced from a constant current provided from a constant current generating circuit, and is subjected to resistance division by a resistance division circuit to produce a reference voltage at the target level, and then a final reference voltage is produced by a voltage follower. An internal voltage generating circuit thus provided can generate the reference voltage having the desired voltage level with high accuracy as well as an internal voltage based on the reference voltage by controlling temperature characteristic even with a low power supply voltage.
摘要翻译： 在从恒定电流产生电路提供的恒定电流中产生高于目标值的电压电压的参考电压，并通过电阻分割电路进行电阻分割以产生目标电平的参考电压，然后 最终的参考电压由电压跟随器产生。 由此提供的内部电压产生电路即使在低电源电压下也可以通过控制温度特性，以高精度产生具有所需电压电平的基准电压以及基于参考电压的内部电压。
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公开(公告)号：US07291538B2
公开(公告)日：2007-11-06
申请号：US11236668
申请日：2005-09-28
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/762
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。
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公开(公告)号：US06965148B2
公开(公告)日：2005-11-15
申请号：US10224317
申请日：2002-08-21
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/786 , H01L31/0312
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。
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89.发明授权Semiconductor integrated circuit device having an internal voltage generation circuit layout easily adaptable to change in specification 失效具有容易适应规格变化的内部电压发生电路布局的半导体集成电路器件公开(公告)号：US06519191B1
公开(公告)日：2003-02-11
申请号：US09696011
申请日：2000-10-26
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G11C700
摘要： An active down converting supplying a large current consumed when a memory array is active, and a Vpp pump for generating a boosted voltage are configured into active units as cells. A required number of active units are provided depending on the array structure and the operation conditions. A power supply circuit can be redesigned and/or rearranged within a short period for adaptation to change in internal structure for the memory array.
摘要翻译： 当存储器阵列处于活动状态时，提供消耗的大电流的有效下变频器和用于产生升压电压的Vpp泵被配置为有源单元作为单元。 根据阵列结构和操作条件，提供所需数量的有效单元。 电源电路可以在短时间内重新设计和/或重新布置，以适应存储器阵列的内部结构的改变。
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90.发明授权Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area 失效半导体存储器件能够在防止芯片面积增加的同时对噪声进行稳定的操作公开(公告)号：US06337506B2
公开(公告)日：2002-01-08
申请号：US09116887
申请日：1998-07-16
申请人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
发明人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
IPC分类号： H01L2900
CPC分类号： H01L23/552 , G11C5/14 , H01L21/761 , H01L23/585 , H01L27/0203 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
摘要翻译： 噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。 提供保护环以至少部分地具有接合焊盘。 利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。
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